c8051t602 Silicon Laboratories, c8051t602 Datasheet - Page 41

• Manufacturer Part Number: c8051t602
• Description: Mixed Signal Otp Eprom Mcu Family
• Manufacturer: Silicon Laboratories

Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bits2–0: AD0CM2–0: ADC0 Start of Conversion Mode Select.
AD0EN
R/W
Bit7
AD0EN: ADC0 Enable Bit.
0: ADC0 Disabled. ADC0 is in low-power shutdown.
1: ADC0 Enabled. ADC0 is active and ready for data conversions.
AD0TM: ADC0 Track Mode Bit.
0: Normal Track Mode: When ADC0 is enabled, a start-of-conversion signal begins the con-
version. For internal conversion start sources, tracking is continuous whenever a conversion
is not in progress. For external CNVSTR signal, tracking of the input occurs when CNVSTR
is held low.
1: Delayed Track Mode: When ADC0 is enabled, input is tracked when a conversion is not
in progress. A start-of-conversion signal initiates three SAR clocks of additional tracking,
and then begins the conversion.
AD0INT: ADC0 Conversion Complete Interrupt Flag.
0: ADC0 has not completed a data conversion since the last time AD0INT was cleared.
1: ADC0 has completed a data conversion.
AD0BUSY: ADC0 Busy Bit.
Read: Unused.
Write:
0: No Effect.
1: Initiates ADC0 Conversion if AD0CM2–0 = 000b
AD0WINT: ADC0 Window Compare Interrupt Flag.
0: ADC0 Window Comparison Data match has not occurred since this flag was last cleared.
1: ADC0 Window Comparison Data match has occurred.
000: ADC0 conversion initiated on every write of ‘1’ to AD0BUSY.
001: ADC0 conversion initiated on overflow of Timer 0.
010: ADC0 conversion initiated on overflow of Timer 2.
011: ADC0 conversion initiated on overflow of Timer 1.
1xx: ADC0 conversion initiated on rising edge of external CNVSTR.
Note : Start of conversion is delayed by three SAR clock cycles when AD0TM = 1.
AD0TM
R/W
Bit6
SFR Definition 5.7. ADC0CN: ADC0 Control
AD0INT AD0BUSY AD0WINT AD0CM2 AD0CM1 AD0CM0 00000000
R/W
Bit5
R/W
Bit4
Rev. 0.5
R/W
Bit3
R/W
Bit2
C8051T600/1/2/3/4/5
R/W
Bit1
Bit Addressable
R/W
Bit0
SFR Address:
Reset Value
0xE8
41