c8051t602 Silicon Laboratories, c8051t602 Datasheet - Page 32

• Manufacturer Part Number: c8051t602
• Description: Mixed Signal Otp Eprom Mcu Family
• Manufacturer: Silicon Laboratories

C8051T600/1/2/3/4/5
5.1.
The analog multiplexer (AMUX0) selects the positive input to the ADC, allowing any Port pin to be mea-
sured relative to GND. Additionally, the on-chip temperature sensor or the positive power supply (V
may be selected as the positive ADC input. The ADC0 input channel is selected in the AMX0SL register as
described in Figure 5.3. When an external Voltage Reference is supplied to P0.0 or the internal regulator is
used as VREF, the V
setting at 0.5x.
Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be config-
ured as analog inputs and should be skipped by the Digital Crossbar. To configure a Port pin for analog
input, clear the corresponding bit in register P0MDIN to ‘0’. To force the Crossbar to skip a Port pin, set the
corresponding bit in register XBR0 to ‘1’. See
I/O configuration details.
5.2.
The ADC has gain settings of 1x and 0.5x. In 1x mode, the full scale reading of the ADC is determined
directly by V
The 0.5x gain setting can be useful to obtain a higher input Voltage range when using a small V
age, or to measure input voltages that are between V
trolled by the AMP0GN1–0 bits in register ADC0CF.
5.3.
The conversion code format for the ADC is shown below. Conversion codes are represented as 10-bit
unsigned integers. Inputs are measured from ‘0’ to V
the ADC0H and ADC0L registers (ADC0H holds the 8 most significant bits, and the two least significant
bits are stored in ADC0L). Example codes are shown below.
5.4.
Setting the ADC08BE bit in register ADC0CF to ‘1’ will put the ADC in 8-bit compatibility mode. This mode
allows backward compatibility with the C8051F300 device family. In 8-bit compatibility mode, only the 8
MSBs of data are converted. The two LSBs of a conversion are always ‘00’ in this mode, and the ADC0L
register will always read back 0x00. 8-bit conversions take two fewer SAR clock cycles than 10-bit conver-
sions, so the conversion is completed faster, and a 500 ksps sampling rate can be achieved with a slower
SAR clock.
32
V
REF
Input Voltage
(AIN – GND),
Gain = 1
V
V
x 1023/1024
8-Bit Compatibility Mode
Analog Multiplexer
Gain Setting
Output Coding
REF
REF
0
REF
/2
/4
. In 0.5x mode, the full-scale reading of the ADC occurs when the input voltage is V
DD
Voltage supply can be determined by taking a measurement of V
10-bit Output (Conversion Code)
0x3FF
0x200
0x100
0x00
Section “13. Port Input/Output” on page 97
Rev. 0.5
REF
REF
x 1023/1024. All conversions are left-justified in
and V
DD
ADC0H:ADC0L Register Coding
. Gain settings for the ADC are con-
0xFF : 0xC0
0x80 : 0x00
0x40 : 0x00
0x00 : 0x00
DD
for more Port
with the gain
REF
REF
volt-
x 2.
DD
)