cop8tab5 National Semiconductor Corporation, cop8tab5 Datasheet
cop8tab5
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cop8tab5 Summary of contents
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... COP8TAB5/TAC5 8-Bit CMOS ROM Microcontroller with Memory 1.0 General Description The COP8TAB5/TAC5 microcontrollers are highly integrated COP8 ™ Feature core devices, with ROM memory and advanced features. These single-chip CMOS devices are suited for applications requiring a full featured controller with moderate memory and low EMI. ...
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Block Diagram 4.0 Ordering Information COP8 TA C Family and Program Feature Set Memory Indicator Size NOTE: The user, utilizing the COP8TAx9 Flash based de- vices during development, is cautioned to ensure that ...
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General Description ..................................................................................................................................... 1 2.0 Features ....................................................................................................................................................... 1 3.0 Block Diagram .............................................................................................................................................. 2 4.0 Ordering Information .................................................................................................................................... 2 5.0 Connection Diagrams ................................................................................................................................... 5 6.0 Architectural Overview ................................................................................................................................. 7 6.1 EMI REDUCTION ...................................................................................................................................... 7 6.2 ARCHITECTURE ..................................................................................................................................... 7 6.3 INSTRUCTION ...
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WATCHDOG AND CLOCK MONITOR SUMMARY .............................................................................. 32 14.4 DETECTION OF ILLEGAL CONDITIONS ............................................................................................ 33 15.0 MICROWIRE/PLUS .................................................................................................................................. 33 15.1 MICROWIRE/PLUS OPERATION ......................................................................................................... 33 15.2 MICROWIRE/PLUS MASTER MODE OPERATION ............................................................................. 34 15.3 MICROWIRE/PLUS SLAVE MODE OPERATION ................................................................................ 34 15.4 ALTERNATE ...
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Connection Diagrams Top View 44 Pin LLP Package See NS Package Number LQA44A Top View 28 Pin Plastic SOIC WIDE Package See NS Package Number M28B 20 Pin Plastic SOIC WIDE Package 20091702 20091704 5 20091705 Top View See ...
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Port Type L0 I/O L1 I/O L2 I/O L3 I/O L4 I/O L5 I/O L6 I/O L7 I/O G0 I/O G1 I/O G2 I/O G3 I/O G4 I I/O C1 I/O C2 I/O ...
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... Architectural Overview 6.1 EMI REDUCTION The COP8TAB5/TAC5 devices incorporate circuitry that guards against electromagnetic interference - an increasing problem in today’s microcontroller board designs. National’s patented EMI reduction technology offers low EMI clock circuitry, gradual turn-on output drivers (GTOs) and internal Icc smoothing filters, to help circumvent many of the EMI issues influencing embedded control designs. National has achieved 15 dB– ...
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Absolute Maximum Ratings 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Voltage at Any Pin ESD Protection Level (Human Body Model) (Machine Model) ...
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Electrical Characteristics AC Electrical Characteristics −40˚C ≤ T specified. Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Parameter Instruction Cycle Time ( Crystal/Resonator, External Internal R/C Oscillator R/C Oscillator Frequency Variation External CKI ...
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... WATCHDOG and clock monitor disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register. CC Note 6: The ACCESS.Bus interface of the COP8TAB5/TAC5 device implements and meets the timings necessary for interface to the I logic levels. The bus drivers are designed with open-drain outputs, as required for proper bidirectional operation. The device will not meet the AC timing and current/voltage drive requirements of the full bus specifications ...
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... Electrical Characteristics 9.0 Pin Descriptions The COP8TAB5/TAC5 I/O structure enables designers to reconfigure the microcontroller’s I/O functions with a single instruction. Each individual I/O pin can be independently configured as output pin low, output high, input with high impedance or input with weak pull-up device. A typical ex- ample is the use of I/O pins as the keyboard matrix input lines ...
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Pin Descriptions FIGURE 5. LLP Package Bottom View CKI is the clock input. This pin can be connected (in con- junction with CKO external crystal circuit to form a crystal oscillator external resistor for RC ...
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Pin Descriptions (Continued) L3 Multi-Input Wake-Up L2 Multi-Input Wake-Up (optional 1.8V compatible input) L1 Multi-Input Wake-Up or ACCESS.Bus Serial Clock (op- tional 1.8V compatible input) L0 Multi-Input Wake-Up or ACCESS.Bus Serial Data (op- tional 1.8V compatible input) FIGURE 6. ...
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... All the CPU registers are memory mapped with the excep- tion of the Accumulator (A) and the Program Counter (PC). Program Memory Device Size (ROM) COP8TAB5 2048 COP8TAC5 4096 10.3 DATA MEMORY The data memory address space includes the on-chip RAM and data registers, the I/O registers (Configuration, Data and Pin), the control registers, the MICROWIRE/PLUS SIO shift register, ACCESS ...
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... After the underflow, the logic is designed such that the C Power On Reset circuit will generate no additional internal resets as long Note: While the POR feature of the COP8TAB5/TAC5 was never intended to function as a brownout detector, there are certain constraints of this 15 20091722 rises ...
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Functional Description (Continued) block that the system designer must address to properly recover from a brownout condition. This is true regardless of whether the internal POR or the external reset feature is used. A brownout condition is reached when ...
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Functional Description With On-Chip Bias Resistor 20091724 With External Frequency Control Resistor (R/C+R) 20091727 10.6.3 External Oscillator The External Oscillator mode can be selected by program- ming Option Bit and Option Bit CKI ...
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Functional Description (Continued) 10.7 CONTROL REGISTERS 10.7.1 CNTRL Register (Address X'00EE) T1C3 T1C2 T1C1 T1C0 MSEL Bit 7 The Timer1 (T1) and MICROWIRE/PLUS control register contains the following bits: T1C3 Timer T1 mode control bit T1C2 Timer T1 mode ...
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Timers (Continued) TABLE 6. Idle Timer Window Length (Continued) ITSEL2 ITSEL1 ITSEL0 Reserved - Undefined Reserved - Undefined Reserved - Undefined The ITSEL bits of the ITMR register are cleared ...
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Timers (Continued) Figure 16 shows a block diagram of the timer in External Event Counter mode. Note: The PWM output is not available in this mode since the T1A pin is being used as the counter input clock. FIGURE ...
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Timers (Continued) 11.5 MODE 3. INPUT CAPTURE MODE The device can precisely measure external frequencies or time external events by placing the timer block, T1, in the input capture mode. In this mode, the reload registers serve as independent ...
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Timers (Continued) 11.6 TIMER CONTROL FLAGS The control bits and their functions are summarized below. T1C3 Timer mode control T1C2 Timer mode control T1C1 Timer mode control T1C0 Timer Start/Stop control in Modes 1 and 2 (Pro- cessor Independent ...
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Power Save Modes second method is with a low to high transition on the CKO (G7) pin. This method precludes the use of the crystal clock configuration (since CKO becomes a dedicated output), and so may only be used ...
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Power Save Modes 12.3 MULTI-INPUT WAKE-UP The Multi-Input Wake-Up feature is used to exit from the HALT and IDLE modes. In addition, the Multi-Input Wake- Up/Interrupt feature may be used to generate edge-selectable external interrupts on ...
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Power Save Modes and LWKPND registers contain undefined values after reset, so software should clear these bits after reset to ensure that no spurious Wake-Up events or interrupts are left pending. 13.0 Interrupts 13.1 INTRODUCTION The device supports eleven ...
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Interrupts (Continued) 13.2 MASKABLE INTERRUPTS All interrupts other than the Software Trap are maskable. Each maskable interrupt has an associated enable bit and pending flag bit. The pending bit is set to 1 when the interrupt condition occurs. The ...
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Interrupts (Continued) sponding to the highest priority enabled and active interrupt. Alternately, the user may choose to poll all interrupt pending and enable bits to determine the source(s) of the interrupt. If more than one interrupt is active, the ...
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Interrupts (Continued) Arbitration Ranking (1) Highest Software (2) Reserved for NMI (3) External (4) Timer T0 (5) Timer T1 (6) Timer T1 (7) MICROWIRE/PLUS (8) ACCESS.Bus (9) Reserved (10) Reserved (11) Reserved (12) Reserved (13) Reserved (14) Reserved (15) ...
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Interrupts (Continued) 13.4 NON-MASKABLE INTERRUPT 13.4.1 Pending Flag There is a pending flag bit associated with the non-maskable Software Trap interrupt, called STPND. This pending flag is not memory-mapped and cannot be accessed directly by the software. The pending ...
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Interrupts (Continued) user program should contain the Software Trap routine to perform a recovery procedure rather than a return to normal execution. Under normal conditions, the STPND flag is reset by a RPND instruction in the Software Trap service ...
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Interrupts (Continued) . SERVICE: RBIT,EXPND,PSW . . . RET I 13.5 PORT C AND PORT L INTERRUPTS Ports C and L provides the user with an additional sixteen fully selectable, edge sensitive interrupts which are all vec- tored into ...
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WATCHDOG/Clock Monitor (Continued) TABLE 9. WATCHDOG Service Window Select (Continued) WDSVR WDSVR Clock Bit 7 Bit 6 Monitor (Lower-Upper Limits 256–32k 256–64k Clock Monitor Disabled ...
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WATCHDOG/Clock Monitor (Continued) • The CLOCK MONITOR detector circuit is active during both the HALT and IDLE modes. Consequently, the de- vice inadvertently entering the HALT mode will be de- tected as a CLOCK MONITOR error (provided that the ...
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MICROWIRE/PLUS mode may cause the current SK clock for the SIO shift register to be narrow. For safety, the BUSY flag should only be set when the input SK clock is in the idle phase. 15.2 MICROWIRE/PLUS MASTER MODE ...
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MICROWIRE/PLUS TABLE 13. MICROWIRE/PLUS Shift Clock Polarity and Sample/Shift Phase Port G SK Phase G6 (SKSEL) Config. Bit Normal 0 Alternate 1 Alternate 0 Normal 1 FIGURE 25. MICROWIRE/PLUS SPI Mode Interface Timing, Normal SK Mode, SK Idle Phase ...
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MICROWIRE/PLUS FIGURE 28. MICROWIRE/PLUS SPI Mode Interface Timing, Alternate SK Mode, SK Idle Phase being High 16.0 ACCESS.Bus Interface The ACCESS.Bus interface module (ACB two-wire serial interface compatible with the ACCESS.Bus physical layer. It permits easy interfacing ...
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ACCESS.Bus Interface (Continued) At each clock cycle, the slave can stall the master while it handles the previous data, or prepares new data. The slave can hold SCL low, to extend the clock-low period, on each bit transfer, or ...
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ACCESS.Bus Interface (Continued) 16.5 ACB SERIAL DATA REGISTER (ACBSDA) The ACBSDA register is a byte-wide, read/write shift register used to transmit and receive data. The most significant bit is transmitted (received) first and the least significant bit is transmitted ...
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ACCESS.Bus Interface (Continued) GCMEN The Global Call Match Enable bit enables the match of an incoming address byte to the general call address (Start Condition followed by address byte of 00) while the ACB is in slave mode. ACK ...
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Memory Map (Continued) Address Contents ADD REG B9 ACB Status Register (ACBST) BA ACB Control And Status (ACBCST) BB ACB Control Register 1 (ACBCTL1) BC ACB Own Address Register (ACBADDR) BD ACB Control Register 2(ACBCTL2 Reserved ...
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Instruction Set (Continued) point to the desired memory location. In the immediate mode, the data byte to be used is contained in the instruction itself. Each addressing mode has its own advantages and disad- vantages with respect to flexibility, ...
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Instruction Set (Continued) Different addressing modes are used to specify the new address for the Program Counter. The choice of addressing mode depends primarily on the distance of the jump. Farther jumps sometimes require more instruction bytes in order ...
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Instruction Set (Continued) 18.4.3 Load and Exchange Instructions The load and exchange instructions write byte values in registers or memory. The addressing mode determines the source of the data. Load (LD) Load Accumulator Indirect (LAID) Exchange (X) 18.4.4 Logical ...
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Instruction Set (Continued) 18.6 INSTRUCTION SET SUMMARY ADD A,Meml ADD ADC A,Meml ADD with Carry SUBC A,Meml Subtract with Carry AND A,Meml Logical AND ANDSZ A,Imm Logical AND Immed., Skip if Zero OR A,Meml Logical OR XOR A,Meml Logical ...
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Instruction Set (Continued) JSRL Addr. Jump SubRoutine Long JSR Addr. Jump SubRoutine JID Jump InDirect RET RETurn from subroutine RETSK RETurn and SKip RETI RETurn from Interrupt INTR Generate an Interrupt NOP No OPeration 18.7 INSTRUCTION EXECUTION TIME Most ...
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Instruction Set (Continued) Register [ (Note 8) 1 (Note 8) 1/1 LD B,Imm LD B,Imm LD Mem,Imm 2/2 LD Reg,Imm IFEQ MD,Imm > Note 8: = Memory location addressed directly. ...
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Nibble Lower 47 www.national.com ...
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... Simulator/ Utilities/ Documentation. Updates from web. Included with COP8-DB-TAC, SKFlash, COP8 Emulators. Eval The ultimate information source for COP8 developers - Integrates with WCOP8 IDE. Organize and manage code, notes, datasheets, etc. M Includes 110v/220v p/s, target cable with 2x7 connector, manuals and software on CD. L For programming 20SOIC COP8TA only ...
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... WCOP8 IDE and Emulator Debugger, with Assembler/ Linker/ CD-ROM Simulators/ Library Manager/ Compiler Demos/ Flash ISP and NiceMon Debugger Utilities/ Example Code/ etc. Includes all COP8 datasheets and documentation. Included with most tools from National. Unis Processor Processor Expert( from Unis Corporation - COP8 Code Generation and Simulation Expert tool with Graphical and Traditional user interfaces ...
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Development Support Programmers for: Design Development; Hardware Test; Pre-Production; Full Production. Product COP8 FLASH COP8 FLASH Emulators include in-circuit device programming capability during Emulators development. NiceMon National’s software Utilities "KANDAFLASH" and "NiceMon" provide Debugger, development In-System-Programming for our FLASH ...
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Development Support Vendor Home Office SofTec Microsystems Via Roma, 1 33082 Azzano Decimo (PN) Italy Tel: +39 0434 640113 Fax: +39 0434 631598 The following companies have approved COP8 programmers in a variety of configurations. Contact your vendor’s local ...
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Revision History Date Section August, 2004 www.national.com Summary of Changes Final Datasheet Release. 52 ...
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... Physical Dimensions Order Number COP8TAB5HLQ8 or COP8TAC5HLQ8 Order Number COP8TAB5EMW8 or COP8TAC5EMW8 inches (millimeters) unless otherwise noted LLP Package NS Package Number LQA44A SOIC Wide Package NS Package Number M28B 53 www.national.com ...
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... Physical Dimensions Order Number COP8TAB5CMW8 or COP8TAC5CMW8 LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or ...