cop8tab5 National Semiconductor Corporation, cop8tab5 Datasheet - Page 32

• Manufacturer Part Number: cop8tab5
• Description: 8-bit Cmos Rom Microcontroller With 2k Or 4k Memory
• Manufacturer: National Semiconductor Corporation

www.national.com
14.0 WATCHDOG/Clock Monitor
14.1 CLOCK MONITOR
The Clock Monitor aboard the device can be selected or
deselected under program control. The Clock Monitor is
guaranteed not to reject the clock if the instruction cycle
clock (1/t
clock input rate on CKI of greater or equal to 100 kHz.
14.2 WATCHDOG/CLOCK MONITOR OPERATION
The WATCHDOG is enabled by bit 2 of the Option Byte.
When this Option bit is 0, the WATCHDOG is enabled and
pin G1 becomes the WATCHDOG output with a weak pullup.
The WATCHDOG and Clock Monitor are disabled during
reset. The device comes out of reset with the WATCHDOG
armed, the WATCHDOG Window Select bits (bits 6, 7 of the
WDSVR Register) set, and the Clock Monitor bit (bit 0 of the
WDSVR Register) enabled. Thus, a Clock Monitor error will
occur after coming out of reset, if the instruction cycle clock
frequency has not reached a minimum specified value, in-
cluding the case where the oscillator fails to start.
The WDSVR register can be written to only once after reset
and the key data (bits 5 through 1 of the WDSVR Register)
must match to be a valid write. This write to the WDSVR
register involves two irrevocable choices: (i) the selection of
the WATCHDOG service window (ii) enabling or disabling of
the Clock Monitor. Hence, the first write to WDSVR Register
involves selecting or deselecting the Clock Monitor, select
the WATCHDOG service window and match the WATCH-
14.3 WATCHDOG AND CLOCK MONITOR SUMMARY
The following salient points regarding the WATCHDOG and
CLOCK MONITOR should be noted:
• Both the WATCHDOG and CLOCK MONITOR detector
• Following RESET, the WATCHDOG and CLOCK MONI-
• The WATCHDOG service window and CLOCK MONI-
WDSVR WDSVR
(Continued)
Bit 7
circuits are inhibited during RESET.
TOR are both enabled, with the WATCHDOG having the
maximum service window selected.
TOR enable/disable option can only be changed once,
during the initial WATCHDOG service following RESET.
1
1
x
x
TABLE 9. WATCHDOG Service Window
C
) is greater or equal to 10 kHz. This equates to a
Bit 6
0
1
x
x
Don’t Care
Don’t Care
Select (Continued)
Mismatch
Monitor
Match
Clock
Data
Key
x
x
0
1
256–32k t
256–64k t
Clock Monitor Disabled
Clock Monitor Enabled
(Lower-Upper Limits)
Don’t Care
Don’t Care
Mismatch
Service Window
Window
Match
Data
C
C
TABLE 10. WATCHDOG Service Actions
Cycles
Cycles
Don’t Care
Don’t Care
Mismatch
Monitor
Clock
Match
32
Valid Service: Restart Service Window
Error: Generate WATCHDOG Output
Error: Generate WATCHDOG Output
Error: Generate WATCHDOG Output
DOG key data. Subsequent writes to the WDSVR register
will compare the value being written by the user to the
WATCHDOG service window value and the key data (bits 7
through 1) in the WDSVR Register. Table 10 shows the
sequence of events that can occur.
The user must service the WATCHDOG at least once before
the upper limit of the service window expires. The WATCH-
DOG may not be serviced more than once in every lower
limit of the service window. The user may service the
WATCHDOG as many times as wished in the time period
between the lower and upper limits of the service window.
The first write to the WDSVR Register is also counted as a
WATCHDOG service.
The WATCHDOG has an output pin associated with it. This
is the WDOUT pin, on pin 1 of the port G. WDOUT is active
low and must be externally connected to the RESET pin or to
some other external logic which handles WATCHDOG event.
The WDOUT pin has a weak pullup in the inactive state. This
pull-up is sufficient to serve as the connection to V
systems which use the internal Power On Reset. Upon
triggering the WATCHDOG, the logic will pull the WDOUT
(G1) pin low for an additional 16 t
signal level on WDOUT pin goes below the lower Schmitt
trigger threshold. After this delay, the device will stop forcing
the WDOUT output low. The WATCHDOG service window
will restart when the WDOUT pin goes high.
A WATCHDOG service while the WDOUT signal is active will
be ignored. The state of the WDOUT pin is not guaranteed
on reset, but if it powers up low then the WATCHDOG will
time out and WDOUT will go high.
The Clock Monitor forces the G1 pin low upon detecting a
clock frequency error. The Clock Monitor error will continue
until the clock frequency has reached the minimum specified
value, after which the G1 output will go high following 16
t
tinual Clock Monitor error if the oscillator fails to start, or fails
to reach the minimum specified frequency. The specification
for the Clock Monitor is as follows:
• The initial WATCHDOG service must match the key data
• Subsequent WATCHDOG services must match all three
• The correct key data value cannot be read from the
• The WATCHDOG detector circuit is inhibited during both
C
–32 t
1/t
1/t
value in the WATCHDOG Service register WDSVR in
order to avoid a WATCHDOG error.
data fields in WDSVR in order to avoid WATCHDOG
errors.
WATCHDOG Service register WDSVR. Any attempt to
read this key data value of 01100 from WDSVR will read
as key data value of all 0’s.
the HALT and IDLE modes.
C
C
>
<
C
10 kHz — No clock rejection.
10 Hz — Guaranteed clock rejection.
clock cycles. The Clock Monitor generates a con-
Action
C
–32 t
C
cycles after the
CC
for