cop8tab5 National Semiconductor Corporation, cop8tab5 Datasheet - Page 18

• Manufacturer Part Number: cop8tab5
• Description: 8-bit Cmos Rom Microcontroller With 2k Or 4k Memory
• Manufacturer: National Semiconductor Corporation

www.national.com
10.0 Functional Description
10.7 CONTROL REGISTERS
10.7.1 CNTRL Register (Address X'00EE)
The Timer1 (T1) and MICROWIRE/PLUS control register
contains the following bits:
10.7.2 PSW Register (Address X'00EF)
The PSW register contains the following select bits:
The Half-Carry flag is also affected by all the instructions that
affect the Carry flag. The SC (Set Carry) and RC (Reset
Carry) instructions will respectively set or clear both the carry
flags. In addition to the SC and RC instructions, ADC, SUBC,
RRC and RLC instructions affect the Carry and Half Carry
flags.
10.7.3 ICNTRL Register (Address X'00E8)
The ICNTRL register contains the following bits:
Bit 7
Bit 7
Unused
(Continued)
T1C3
T1C3
T1C2
T1C1
T1C0
MSEL
IEDG
SL1 & SL0 Select the MICROWIRE/PLUS clock divide
Bit 7
HC
C
T1PNDA Timer T1 Interrupt Pending Flag (Autoreload RA
T1ENA
EXPND
BUSY
EXEN
GIE
LPEN
T0PND
T0EN
µWPND MICROWIRE/PLUS interrupt pending
µWEN
T1PNDB Timer T1 Interrupt Pending Flag for T1B capture
HC
T1C2
C
LPEN
Half Carry Flag
Carry Flag
in mode 1, T1 Underflow in Mode 2, T1A capture
edge in mode 3)
Timer T1 Interrupt Enable for Timer Underflow
or T1A Input capture edge
External interrupt pending
MICROWIRE/PLUS busy shifting flag
Enable external interrupt
Global interrupt enable (enables interrupts)
L/C
Wake-Up/Interrupt)
Timer T0 Interrupt pending
Timer T0 Interrupt Enable (Bit 12 toggle)
Enable MICROWIRE/PLUS interrupt
edge
T1PNDA
Timer T1 mode control bit
Timer T1 mode control bit
Timer T1 mode control bit
Timer
modes 1 and 2. T1 Underflow Interrupt
Pending Flag in timer mode 3
Selects G5 and G4 as MICROWIRE/PLUS
signals SK and SO respectively
External
(0 = Rising edge, 1 = Falling edge)
by (00 = 2, 01 = 4, 1x = 8)
T1C1
T0PND
Port
T1ENA
T1C0
T1
T0EN
interrupt
Interrupt
Start/Stop
µWPND
MSEL
EXPND
edge
µWEN
Enable
IEDG
BUSY
control
polarity
T1PNDB
SL1
EXEN
(Multi-Input
in
T1ENB
select
SL0
timer
Bit 0
GIE
Bit 0
Bit 0
18
10.7.4 ITMR Register (Address X'00CF)
The ITMR register contains the following bits:
11.0 Timers
The device contains a very versatile set of timers (T0 and
T1). Timer T1 and associated autoreload/capture registers
power up containing random data.
11.1 TIMER T0 (IDLE TIMER)
The device supports applications that require maintaining
real time and low power with the IDLE mode. This IDLE
mode support is furnished by the IDLE Timer T0, which is a
16-bit timer. The user cannot read or write to the IDLE Timer
T0, which is a count down timer.
The clock to the IDLE Timer is the instruction cycle clock
(one-tenth of the CKI frequency).
In addition to its time base function, the Timer T0 supports
the following functions:
• Exit out of the Idle Mode (See Idle Mode description)
• WATCHDOG logic (See WATCHDOG description)
• Start up delay out of the HALT mode
• Start up delay from POR
is a functional block diagram showing the structure of the
IDLE Timer and its associated interrupt logic.
Bits 11 through 15 of the ITMR register can be selected for
triggering the IDLE Timer interrupt. Each time the selected
bit underflows (every 4k, 8k, 16k, 32k or 64k selected
clocks), the IDLE Timer interrupt pending bit T0PND is set,
thus generating an interrupt (if enabled), and bit 6 of the Port
G data register is reset, thus causing an exit from the IDLE
mode if the device is in that mode.
In order for an interrupt to be generated, the IDLE Timer
interrupt enable bit T0EN must be set, and the GIE (Global
Interrupt Enable) bit must also be set. The T0PND flag and
T0EN bit are bits 5 and 4 of the ICNTRL register, respec-
tively. The interrupt can be used for any purpose. Typically, it
is used to perform a task upon exit from the IDLE mode. For
more information on the IDLE mode, refer to Section 12.2
IDLE MODE .
The Idle Timer period is selected by bits 0–2 of the ITMR
register Bit 3 of the ITMR Register is reserved and should
not be used as a software flag. Bits 4 through 7 of the ITMR
Register are reserved and must be zero.
Bit 7
T1ENB
RSVD
ITSEL2 Idle Timer period select bit.
ITSEL1 Idle Timer period select bit.
ITSEL0 Idle Timer period select bit.
ITSEL2
0
0
0
0
1
TABLE 6. Idle Timer Window Length
These bits are reserved and must be 0.
Timer T1 Interrupt Enable for T1B Input capture
edge
ITSEL1
RSVD
0
0
1
1
0
ITSEL0
0
1
0
1
0
ITSEL2
16,384 inst. cycles
32,768 inst. cycles
65,536 inst. cycles
Idle Timer Period
4,096 inst. cycles
8,192 inst. cycles
ITSEL1
ITSEL0
Bit 0