cop8tab5 National Semiconductor Corporation, cop8tab5 Datasheet - Page 31

• Manufacturer Part Number: cop8tab5
• Description: 8-bit Cmos Rom Microcontroller With 2k Or 4k Memory
• Manufacturer: National Semiconductor Corporation

13.0 Interrupts
SERVICE:
13.5 PORT C AND PORT L INTERRUPTS
Ports C and L provides the user with an additional sixteen
fully selectable, edge sensitive interrupts which are all vec-
tored into the same service subroutine.
The interrupt from Ports C and L share logic with the
wake-up circuitry. The registers CWKEN and LWKEN allow
interrupts from Ports C and L to be individually enabled or
disabled. The register CWKEDG and LWKEDG specify the
trigger condition to be either a positive or a negative edge.
Finally, the registers CWKPND and LWKPND latch in the
pending trigger conditions.
The GIE (Global Interrupt Enable) bit enables the interrupt
function.
A control flag, LPEN, functions as a global interrupt enable
for Port C and Port L interrupts. Setting the LPEN flag will
enable interrupts and vice versa. A separate global pending
flag is not needed since the registers CWKPND and LWK-
PND are adequate.
Since Ports C and L are also used for waking the device out
of the HALT or IDLE modes, the user can elect to exit the
HALT or IDLE modes either with or without the interrupt
enabled. If he elects to disable the interrupt, then the device
will restart execution from the instruction immediately follow-
ing the instruction that placed the microcontroller in the
HALT or IDLE modes. In the other case, the device will first
execute the interrupt service routine and then revert to nor-
mal operation.
13.6 INTERRUPT SUMMARY
The device uses the following types of interrupts, listed
below in order of priority:
1. The Software Trap non-maskable interrupt, triggered by
2. Maskable interrupts, triggered by an on-chip peripheral
3. While executing from the Boot ROM for ISP or virtual E2
the INTR (00 opcode) instruction. The Software Trap is
acknowledged immediately. This interrupt service rou-
tine can be interrupted only by another Software Trap.
The Software Trap should end with two RPND instruc-
tions followed by a re-start procedure.
block or an external device connected to the device.
Under ordinary conditions, a maskable interrupt will not
interrupt any other interrupt routine in progress. A
maskable interrupt routine in progress can be inter-
rupted by the non-maskable interrupt request. A
maskable interrupt routine should end with an RETI
instruction or, prior to restoring context, should return to
execute the VIS instruction. This is particularly useful
when exiting long interrupt service routines if the time
between interrupts is short. In this case the RETI instruc-
tion would only be executed when the default VIS rou-
tine is reached.
operations, the hardware will disable interrupts from oc-
curring. The hardware will leave the GIE bit in its current
state, and if set, the hardware interrupts will occur when
execution is returned to ROM Memory. Subsequent in-
.
RBIT,EXPND,PSW
.
.
.
RET I
(Continued)
; Interrupt Service Routine
; Reset ext interrupt pend. bit
; Return, set the GIE bit
31
14.0 WATCHDOG/Clock Monitor
The devices contain a user selectable WATCHDOG and
clock monitor. The following section is applicable only if
WATCHDOG feature has been selected in the Option Byte.
The WATCHDOG is designed to detect the user program
getting stuck in infinite loops resulting in loss of program
control or “runaway” programs.
The WATCHDOG logic contains two separate service win-
dows. While the user programmable upper window selects
the WATCHDOG service time, the lower window provides
protection against an infinite program loop that contains the
WATCHDOG service instruction.
The COP8TAx devices provide the added feature of a soft-
ware trap that provides protection against stack overpops
and addressing locations outside valid user program space.
The Clock Monitor is used to detect the absence of a clock or
a very slow clock below a specified rate on the CKI pin.
The WATCHDOG consists of two independent logic blocks:
WD UPPER and WD LOWER. WD UPPER establishes the
upper limit on the service window and WD LOWER defines
the lower limit of the service window.
Servicing the WATCHDOG consists of writing a specific
value to a WATCHDOG Service Register named WDSVR
which is memory mapped in the RAM. This value is com-
posed of three fields, consisting of a 2-bit Window Select, a
5-bit Key Data field, and the 1-bit Clock Monitor Select field.
Table 8 shows the WDSVR register.
The lower limit of the service window is fixed at 256 instruc-
tion cycles. Bits 7 and 6 of the WDSVR register allow the
user to pick an upper limit of the service window.
Table 9 shows the four possible combinations of lower and
upper limits for the WATCHDOG service window. This flex-
ibility in choosing the WATCHDOG service window prevents
any undue burden on the user software.
Bits 5, 4, 3, 2 and 1 of the WDSVR register represent the
5-bit Key Data field. The key data is fixed at 01100. Bit 0 of
the WDSVR Register is the Clock Monitor Select bit.
WDSVR WDSVR
Bit 7
TABLE 8. WATCHDOG Service Register (WDSVR)
terrupts, during ISP operation, from the same interrupt
source will be lost.
X
0
0
Window
TABLE 9. WATCHDOG Service Window Select
Select
X
Bit 6
0
1
0
Monitor
Clock
x
x
1
Key Data
1
256–8k t
256–16k t
(Lower-Upper Limits)
Service Window
0
C
C
Cycles
0
Cycles
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Monitor
Clock
Y