ak5355 AKM Semiconductor, Inc., ak5355 Datasheet - Page 10

• Manufacturer Part Number: ak5355
• Description: Low Power 16bit ?? Adc
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
The clocks required to operate are MCLK (256fs/384fs/512fs), LRCK (fs) and BCLK (32fs∼). The master clock (MCLK)
should be synchronized with LRCK. The phase between these clocks does not matter. The frequency of MCLK can be
input as 256fs, 384fs or 512fs. When the 384fs or 512fs is input, the internal master clock is divided into 2/3 or 1/2
automatically.
*fs is sampling frequency.
All external clocks (MCLK, BCLK and LRCK) should always be present whenever the ADC is in operation. If these
clocks are not provided, the AK5355 may draw excess current and will not operate properly because it utilizes these
clocks for internal dynamic refresh of registers. If the external clocks are not present, the AK5355 should be placed in
power-down mode.
The SDTO, BCLK and LRCK pins are connected to an external controller. The audio data format has two modes,
MSB-first and 2’s compliment. The data format is set using the DIF pin.
MS0113-E-01
BCLK(32fs)
SDTO(o)
BCLK(64fs)
SDTO(o)
LRCK
System Clock
Audio Data I/F Format
LRCK
BCLK(32fs)
SDTO(o)
BCLK(64fs)
SDTO(o)
0
0
No.
15:MSB, 0:LSB
15
15
0
1
0
0
1
1
0
14
14
1
1
DIF pin
15:MSB, 0:LSB
15
15
2
2
13
13
H
L
2
2
3
3
14
14
3
3
8
13
8
13
13
4
4
7
2
16bit MSB justified
9
14
Lch Data
7
I
SDTO (ADC)
2
6
1
9
14
S Compatible
10
15
2
7
Figure 4. Audio Data Timing (No.0)
5
0
10
15
Lch Data
Figure 5. Audio Data Timing (No. 1)
11
16
6
1
Table 1. Audio Data Format
OPERATION OVERVIEW
11
16
4
12
17
0
5
3
12
17
13
18
4
2
13
18
14
3
- 10 -
1
14
Lch: “H”, Rch: “L”
Lch: “L”, Rch: “H”
15
31
2
0
15
31
0
0
1
LRCK
15 14
15 14
0
0
1
1
0
1
1
15
15
2
2
13
13
2
2
3
3
14
14
3
3
8
1
8
13
13
4
7
2
4
BCLK
≥ 32fs
≥ 32fs
9
14
Rch Data
7
2
6
1
9
14
10
15
2
7
5
0
10
15
Rch Data
11
16
6
1
11
16
Figure 4
Figure 5
4
Figure
12
17
0
5
3
12
17
13
18
4
2
13
18
14
3
1
14
15
31
2
[AK5355]
0
15
31
2005/01
0
0
1
15
15
0
0
1
1
0
1
1