ak4366 AKM Semiconductor, Inc., ak4366 Datasheet - Page 11

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ak4366

Manufacturer Part Number
ak4366
Description
Low Power 24-bit 2ch Dac With Hp-amp
Manufacturer
AKM Semiconductor, Inc.
Datasheet

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DFS1
ASAHI KASEI
The external clocks required to operate the AK4366 are MCLK(256fs/384fs/512fs), LRCK(fs) and BICK. The master
clock (MCLK) should be synchronized with sampling clock (LRCK). The phase between these clocks does not matter.
The frequency of MCLK is detected automatically, and the internal master clock becomes the appropriate frequency.
Table 1 shows system clock example.
In serial mode (P/S pin = “L”), all external clocks (MCLK, BICK and LRCK) should always be present whenever the
DAC is in normal operation mode (PMDAC bit = “1”). If these clocks are not provided, the AK4366 may draw excess
current and will not operate properly because it utilizes these clocks for internal dynamic refresh of registers. If the
external clocks are not present, the DAC should be placed in power-down mode (PMDAC bit = “0”). When MCLK is
input with AC coupling, the MCKAC bit should be set to “1”.
In parallel mode (P/S pin = “H”), all external clocks (MCLK, BICK and LRCK) should always be present whenever the
DAC is in normal operation mode (PDN pin = “H”). If these clocks are not provided, the AK4366 may draw excess
current and will not operate properly because it utilizes these clocks for internal dynamic refresh of registers. If the
external clocks are not present, the DAC should be placed in power-down mode (PDN pin = “L”).
For low sampling rates, DR and S/N degrade because of the outband noise. In serial mode (P/S pin = “L”), DR and S/N
are improved by setting DFS1 bit to “1”. Table 2 shows S/N of HP-amp output. When the DFS1 bit is “1”, MCLK needs
512fs.
MS0248-E-01
0
0
1
System Clock
DFS0
0
1
x
Over Sample
Table 2. Relationship among fs, MCLK frequency and S/N of HP-amp
11.025kHz
128fs
256fs
22.05kHz
Rate
64fs
44.1kHz
LRCK
12kHz
16kHz
24kHz
32kHz
48kHz
8kHz
fs
8kHz∼48kHz
8kHz∼24kHz
8kHz∼12kHz
11.2896
2.8224
5.6448
12.288
Table 1. System Clock Example
256fs
2.048
3.072
4.096
6.144
8.192
OPERATION OVERVIEW
fs
MCLK (MHz)
16.9344
4.2336
8.4672
12.288
18.432
384fs
3.072
4.608
6.144
9.216
256fs/384fs/512fs
256fs/384fs/512fs
- 11 -
MCLK
512fs
11.2896
22.5792
5.6448
12.288
16.384
24.576
512fs
4.096
6.144
8.192
S/N (fs=8kHz, A-weighted)
BICK (MHz)
0.7056
1.4112
2.8224
0.512
0.768
1.024
1.536
2.048
3.072
64fs
HP-amp
56dB
75dB
92dB
[AK4366]
2004/03
Default

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