ak4373 ETC-unknow, ak4373 Datasheet
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ak4373 Summary of contents
Page 1
... The AK4373 is a low power stereo 24bit DAC with an integrated stereo headphone amplifier and a monaural speaker driver. It can be used for a variety of portable audio and media player applications, including game consoles, dedicated headphone drivers, personal navigation devices, and portable media players. The output drivers can be configured for three unique use cases: mono speaker driver or single-ended ac-coupled headphones which can be used as stereo line-out, DC-coupled BTL headphones and Pseudo Cap-less ...
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... VOL DACS SPKG[1:0] VOL PMSPK MINS MINH PMMIN HVDD VSS2 - 2 - VSS3 DVDD Control Register Digital Processing - HPF Audio - LPF DATT - 3D Enhance I/F SMUTE - Frequency Compensation - 5-BiQuads - ALC/Limiter PLL PMPLL [AK4373] I2C CAD0/CSN SCL/CCLK SDA/CDTI PDN BICK LRCK SDTI MCKO MCKI VCOC 2008/09 ...
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... PLL PMPLL DVDD VSS3 Control Register Digital Processing - HPF Audio - LPF DATT I Enhance SMUTE - Frequency Compensation - 5-BiQuads - ALC/Limiter PLL PMPLL [AK4373] I2C CAD0/CSN SCL/CCLK SDA/CDTI PDN PDN BICK LRCK SDTI MCKO MCKI VCOC I2C CAD0/CSN SCL/CCLK SDA/CDTI PDN BICK LRCK SDTI ...
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... AK4373EN AKD4373 ■ Pin Layout MUTET 25 ROUT 26 LOUT 27 MIN+ 28 MIN MS0991-E-00 −30 ∼ +85°C 32pin QFN (0.5mm pitch) Evaluation board for AK4373 AK4373EN Top View - 4 - [AK4373] VSS3 16 DVDD 15 BICK 14 LRCK SDTI CDTI / SDA 10 CCLK / SCL 9 2008/09 ...
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... Comparison table between AK4343 and AK4373 1. Function Function DAC Resolution HP-Amp S/N HP-Amp Output Type Five Programmable Biquads Line Output Pins MCKI Input Level Analog Mixing Receiver Amp SPK AMP 2. Pin Pin MS0991-E-00 AK4343 ...
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... F2A7 F2A6 F2A5 0 0 F2A13 F2A12 F2B7 F2B6 F2B5 0 0 F2B13 F2B12 These bits were added to the AK4373. These bits were removed from the AK4343. These bits name were changed PMLO PMDAC M/S MCKAC MCKO HPBTL PMMP PSEUDO SPKG0 ...
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... E5A12 E5B7 E5B6 E5B5 E5B4 E5B15 E5B14 E5B13 E5B12 E5C7 E5C6 E5C5 E5C4 E5C15 E5C14 E5C13 E5C12 These bits were added to the AK4373. These bits were removed from the AK4343 EQ4 EQ3 EQ2 E1A3 E1A2 E1A1 E1A11 ...
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... C Bus, “L”: 3-wire Serial Power-Down Mode Pin “H”: Power-up, “L”: Power-down, reset and initialization of the control register. The AK4373 must be reset once upon power-up. Chip Select Pin (I2C pin = “L”: 3-wire Serial Mode) Chip Address 1 Select Pin (I2C pin = “H”: I Control Data Clock Pin (I2C pin = “ ...
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... If the MIN+ pin is used as single-ended, this pin should be connected to the VSS1 with a capacitor. No Connect Pin No internal bonding. This pin should be open or connected to the ground. No Connect Pin No internal bonding. This pin should be open or connected to the ground. No Connect Pin No internal bonding. This pin should be open or connected to the ground Function [AK4373] 2008/09 ...
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... Note 9. In case that the exposed pad is connected to the ground and PCB drawing density is 100%.This power is the AK4373 internal dissipation that does not include power of externally connected speaker and headphone. WARNING: Operation at or beyond these limits may result in permanent damage to the device. ...
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... HPBTL bit = “0”, =10kΩ, ALC=OFF, L 1.98 2. Point RL typ max (Figure 5), HPBTL bit = “0”, =22.8Ω, ALC=OFF, L 1.98 2.38 3. 300 [AK4373] Units Bits Vpp kΩ pF Units Vpp Vpp Vrms Ω 2008/09 ...
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... =32Ω. L HPL+/HPR+ pin R1 C1 Measurement Point HPL-/HPR- pin Point R2 C2 typ max mode(Figure 6), HPBTL bit = “1”, =32Ω, ALC=OFF, L 3. 300 [AK4373] Units Vpp Vrms Ω 2008/09 ...
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... PSEUDO bit = “1” , HPG bit = “0”, HVDD=3.3V, R AVOL=0dB, DVOL=0dB; unless otherwise specified. - (Note 18 (Note 18 =16Ω. L HPL/HPR pin R1 C1 Measurement Point HVCM pin [AK4373] typ max Units mode(Figure 7), HPBTL bit = “0”, =22.8Ω, ALC=OFF, L 1.98 - 0.98 - Vrms ...
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... ALC bit = “1”, SPKG1-0 bits = “10” ALC bit = “1”, SPKG1-0 bits = “11” MS0991-E-00 min - 3. =20Ω BTL, HVDD=3.8V; unless otherwise specified. (Figure 53) series - - -0. [AK4373] typ max =8Ω, BTL, L 3.11 - 3.92 4.71 2. =3μ ...
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... Vin = (MIN+) – (MIN-) = 0.6 x AVDD x 20kΩ (typ)/Rin. The signals with same amplitude and inverted phase should be input to MIN+ and MIN- pins, respectively. MS0991-E- +9.6 -0.07 +4.43 - +6.43 - +10.65 - +12.65 - +6.43 - +8.43 - +12.65 - +14.65 ) and piezo speaker impedance at 1kHz in series - 15 - [AK4373] - Vpp - +8. Figure 2008/09 ...
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... SPK Table 1. Power Consumption for each operation mode (typ) MS0991-E-00 min - - - 27) - 28) 29) - Typical Current 01H AVDD DVDD [V] [mA] [ 3.3 0 3.3 2.2 2.7 1 3.3 3.1 3.3 2.2 2.7 1 3.3 3.2 3 typ max 7.8 - 8.1 12 2 Total Power HVDD [mA] [V] [mA] [mW] 0 3.3 0 2.2 1.9 11.9 1.0 4.0 2.6 18.1 2.7 3.3 2.2 26.4 2.2 4.2 17.0 1.0 4.0 5.2 28.5 2.7 3.3 4.1 33.0 [AK4373] Units μA 0 2008/09 ...
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... VIH 70%DVDD VIH 80%DVDD VIL VIL 32) VAC VOH DVDD−0.2 VOL VOL VOL Iin (Figure typ max - 20.0 22. ±0. ±1.0 - typ max - - - - - - 30%DVDD - - 20%DVDD 20%DVDD ± [AK4373] Units kHz kHz kHz dB dB 1/fs dB Units Vpp μA 2008/09 ...
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... Duty 45 tBCK 1/(64fs) tBCKL 0.4 x tBCK tBCKH 0.4 x tBCK - 18 - [AK4373] =20pF; unless otherwise specified) L typ max Units - 27 MHz - - - - - - - 12.288 MHz kHz tBCK - 50 - 1/(32fs) - 1/(64fs) ...
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... Duty - 50 tBCK - 1/(32fs) tBCK - 1/(64fs) dBCK - [AK4373] max Units 48 kHz 1/fs − tBCK 1/(32fs kHz 1/fs − tBCK 12.288 MHz 13.312 MHz 13.312 MHz ...
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... S) −40 35) tMBLR tSDH 50 tSDS 50 35) tLRB 50 tBLR 50 35) tSDH 50 tSDS [AK4373] typ max Units 0.5 x tBCK 0.5 x tBCK + 40 0.5 x tBCK 0.5 x tBCK + 2008/ ...
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... registered trademark of Philips Semiconductors. Note 37. CCLK rising edge must not occur at the same time as CSN edge. Note 38. Data must be held long enough to bridge the 300ns-transition time of SCL. Note 39. The AK4373 can be reset by the PDN pin = “L”. ■ Timing Diagram ...
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... Duty = tLRCKH 100 1/fMCK tMCKL dMCK = tMCKL x fMCK x 100 Figure 9. Clock Timing (PLL/EXT Master mode) tLRCKH tBCK tDBF tSDS - 22 - VIH VIL 50%DVDD tLRCKL 100 50%DVDD 50%DVDD dBCK 50%DVDD 50%DVDD tSDH VIH VIL [AK4373] 2008/09 ...
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... Figure 11. Audio Interface Timing (PLL/EXT Master mode, DSP mode, MSBS = “1”) LRCK BICK SDTI Figure 12. Audio Interface Timing (PLL/EXT Master mode, Except DSP mode) MS0991-E-00 tLRCKH tBCK tDBF dBCK tSDS tBLR tSDS tSDH - 23 - 50%DVDD 50%DVDD 50%DVDD tSDH VIH VIL 50%DVDD tBCKL 50%DVDD VIH VIL [AK4373] 2008/09 ...
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... Figure 14. Clock Timing (PLL Slave mode; PLL Reference Clock = LRCK or BICK pin, DSP mode, MSBS = “1”) MS0991-E-00 1/fs tLRCKH tBCK tBCKH tBCKL 1/fs tLRCKH tBCK tBCKH tBCKL - 24 - [AK4373] VIH VIL tBLR VIH VIL VIH VIL VIH VIL tBLR VIH VIL VIH ...
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... Duty = tLRCKH 100 tBCK tBCKH tBCKL fMCK tMCKL dMCK = tMCKL x fMCK x 100 tLRCKH tLRB tSDS MSB - 25 - VIH VIL VIH VIL = tLRCKL 100 VIH VIL 50%DVDD VIH VIL VIH VIL VIH VIL tSDH VIH VIL [AK4373] 2008/09 ...
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... MS0991-E-00 tLRCKH tLRB tSDS 1/fCLK tCLKH tCLKL 1/fs Duty = tLRCKH 100 tLRCKH tLRCKL tBCK tBCKH tBCKL Figure 18. Clock Timing (EXT Slave mode [AK4373] VIH VIL VIH VIL VIH VIL tSDH VIH MSB VIL VIH VIL VIH VIL tLRCKL 100 VIH ...
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... A6 A5 Figure 20. WRITE Command Input Timing tCSH D1 D0 Figure 21. WRITE Data Input Timing - 27 - VIH VIL VIH VIL VIH VIL VIH VIL tCCKH VIH VIL tCCK tCDH VIH R/W VIL tCSW VIH VIL tCSS VIH VIL VIH VIL [AK4373] 2008/09 ...
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... SDA tBUF tLOW SCL tHD:STA Stop Start PDN MS0991-E-00 tHIGH tR tF tHD:DAT tSU:DAT tSU:STA Start 2 Figure 22 Bus Mode Timing tPD Figure 23. Power Down & Reset Timing - 28 - [AK4373] VIH VIL tSP VIH VIL tSU:STO Stop VIL 2008/09 ...
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... AK4373 goes to master mode by changing M/S bit = “1”. When the AK4373 is in master mode, LRCK and BICK pins are a floating state until M/S bit becomes “1”. LRCK and BICK pins of the AK4373 should be pulled-down or pulled- resistor (about 100kΩ) externally to avoid the floating state ...
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... Others Table 7. Setting of Sampling Frequency at PLL2 bit = “0” and PMPLL bit = “1” PLL Slave Mode 2 MS0991-E-00 Table 5, whenever the AK4373 is supplied to a stable clocks after PLL0 PLL Reference Input bit Clock Input Pin Frequency 0 LRCK pin 1fs ...
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... MCKO bit = “0” “1” “L” Output “L” Output “L” Output - 31 - BICK pin LRCK pin “L” Output “L” Output Invalid Invalid See Table 11 1fs Output MCKO pin MCKO bit = “1” Invalid Invalid Output [AK4373] 2008/09 ...
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... Figure 24. PLL Master Mode PS1 bit PS0 bit BICK Output BCKO bit Frequency 0 32fs 1 64fs Table 11. BICK Output Frequency at Master Mode - 32 - DSP or μP MCLK BCLK LRCK SDTO MCKO pin 256fs (default) 128fs 64fs 32fs (default) [AK4373] 2008/09 ...
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... PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”) A reference clock of PLL is selected among the input clocks to the MCKI, BICK or LRCK pin. The required clock to the AK4373 is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits a) PLL reference clock: MCKI pin BICK and LRCK inputs must be synchronized with MCKO output ...
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... The external clocks (BICK and LRCK) must always be present whenever the DAC is in operation (PMDAC bit = “1”). If these clocks are not provided, the AK4373 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If the external clocks are not present, the DAC must be in the power-down mode (PMDAC bit = “ ...
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... EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”) When PMPLL bit is “0”, the AK4373 changes to EXT mode. Master clock is input from the MCKI pin, the internal PLL circuit is not operated. This mode is compatible with I normal audio DAC. The clocks required to operate are MCKI (256fs, 512fs or 1024fs), LRCK (fs) and BICK (≥ ...
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... EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”) The AK4373 becomes EXT Master Mode by setting PMPLL bit = “0” and M/S bit = “1”. Master clock is input from the MCKI pin, the internal PLL circuit is not operated. The clock required to operate is MCKI (256fs, 512fs or 1024fs). The ...
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... Three types of data formats are available and are selected by setting the DIF1-0 bits data is MSB first, 2’s complement format. Audio interface formats can be used in both master and slave modes. LRCK and BICK are output from the AK4373 in master mode, but must be input to the AK4373 in slave mode. Mode ...
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... BICK after the rising edge (“↑”) of LRCK. MSB of SDTI is latched by the 2nd rising edge (“↑”) of the 1 BICK after the rising edge (“↑”) of LRCK.. Table 20. Audio Interface Format in Mode [AK4373] Figure Figure 38 (default) Figure 39 Figure 40 ...
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... [AK4373 2008/09 ...
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... Don’t care Lch Data Figure 35. Mode 4, 5 Timing - Rch Rch Data Rch Data [AK4373 2008/09 ...
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... Figure 37. Mode 3 Timing - 41 - Rch Don’t 0 care Don’ care Don’ care Rch Don’ care Don’ care Don’ care [AK4373 2008/09 ...
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... Rch 1/ Rch 1/ [AK4373 2008/09 ...
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... Rch 1/ Rch 1/ [AK4373 2008/09 ...
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... Digital EQ/HPF/LPF The AK4373 performs high/low pass filter, stereo separation emphasis, gain compensation, five programmable biquads, ALC (Automatic Level Control) and digital volume by digital domain for input data st blocks are IIR filters of 1 order. The filter coefficient of HPF, LPF, FIL3, and EQ blocks can be set to any value. ...
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... Amplitude 2 − 2cos (2πf/fs 2Bcos (2πf/fs) 1 − tan (πfc/fs tan (πfc/fs) Amplitude 2 + 2cos (2πf/fs 2Bcos (2πf/fs [AK4373] Phase (B+1)sin (2πf/fs) −1 θ(f) = tan (B−1)cos (2πf/fs) Phase (B−1)sin (2πf/fs) −1 θ(f) = tan (B+1)cos (2πf/fs) 2008/09 ...
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... Amplitude 2 − 2cos (2πf/fs) θ(f) = tan 2Bcos (2πf/fs) 1 − tan (πfc/fs tan (πfc/fs) Amplitude 2 + 2cos (2πf/fs) θ(f) = tan 2Bcos (2πf/fs [AK4373] Phase (B+1)sin (2πf/fs) − (B−1)cos (2πf/fs) Phase (B−1)sin (2πf/fs) − (B+1)cos (2πf/fs) 2008/09 ...
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... MS0991-E-00 1 − tan (πfc /fs) /fs /fs tan (πfc /fs Amplitude 2ACcos (2πf/fs 2Bcos (2πf/fs − tan (π tan (πfc Phase (AB−C)sin (2πf/fs) −1 θ(f) = tan (AB+C)cos (2πf/fs) 13 [AK4373] /fs) 2 /fs) 1 2008/09 ...
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... F3A[13:0] bits = 00 0011 1010 0010 F3B[13:0] bits = 10 1110 1000 0000 4) EQ block Example: fs=44.1kHz, fc =300Hz Gain[dB] +8dB fc EQA[15:0] bits = 0000 1001 0110 1110 EQB[13:0] bits = 10 0001 0101 1001 EQC[15:0] bits = 1111 1001 1110 1111 MS0991-E-00 =3000Hz, Gain=+8dB 2 fc Frequency [AK4373] 2008/09 ...
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... MS0991-E-00 , E1C[15:0] bits = E2C[15:0] bits = E3C[15:0] bits = E4C[15:0] bits = E5C[15:0] bits = cos(2π fo /fs tan (π − tan (π /fs tan (π [AK4373] /fs) n /fs) n 2008/09 ...
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... Table 24. ALC Zero Crossing Timeout Period - 50 - [AK4373] (Table 22), the AVL and (Table 24). When ALC output level exceeds (Table (default) (default) 44.1kHz 2.9ms (default) 5.8ms 11.6ms 23.2ms 23). 22) ...
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... Table 26. ALC Recovery GAIN Step - 51 - (Table 22) during the wait time, ALC recovery (Table (Table 16kHz 44.1kHz 8ms 2.9ms (default) 16ms 5.8ms 32ms 11.6ms 64ms 23.2ms 128ms 46.4ms 256ms 92.9ms 512ms 185.8ms 1024ms 371.5ms 0.375dB (default) 0.750dB 1.125dB 1.500dB [AK4373] 26 the 24). Then 2008/09 ...
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... Table 27. Reference Level at ALC Recovery operation RFST1 bit Table 28. Fast Recovery Speed Setting (N/A: not available) MS0991-E-00 GAIN(dB) +36.0 +35.625 +35. +30.375 +30.0 +29.625 : : −53.25 −53.625 −54.0 MUTE RFST0 bit Recovery Speed Step 0.375dB (default) 4 times (default) 8 times 16times N/A [AK4373] 2008/09 ...
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... Operation −4.1dBFS 001 E1H E1H Table 29. Example of the ALC setting Example: * The value of AVOL should be the same or smaller than REF’ [AK4373] fs=44.1kHz Data Operation −4.1dBFS 01 Enable 0 Enable 32ms 11 23.2ms 32ms 011 23.2ms +30dB E1H +30dB ...
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... When ALC is not used, AVL7-0 and AVR7-0 bits should be set to “91H” (0dB). AVL7-0 AVR7-0 F1H F0H EFH : E2H E1H E0H : 03H 02H 01H 00H MS0991-E-00 GAIN (dB) +36.0 +35.625 +35.25 : +30.375 0.375dB +30.0 +29.625 : −53.25 −53.625 −54 MUTE Table 30. ALC Block Digital Volume Setting - 54 - (Table 30). The AVOL value is changed at Step (default) [AK4373] 2008/09 ...
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... ALC bit = “0”. MS0991-E-00 Disable Enable E1H(+30dB) C6H(+20dB) E1H(+30dB) E1(+30dB) --> F1(+36dB) (1) C6H(+20dB) E1(+30dB) --> F1(+36dB) Figure 48. AVOL value during ALC operation - 55 - [AK4373] Disable E1(+30dB) (2) C6H(+20dB) 2008/09 ...
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... Digital Output Volume The AK4373 has a digital output volume (256 levels, 0.5dB step, Mute). The volume can be set by the DVL7-0 and DVR7-0 bits. The volume is included in front of a DAC block. The input data of DAC is changed from +12 to –115dB or MUTE. When the DVOLC bit = “1”, the DVL7-0 bits control both Lch and Rch attenuation levels. When the DVOLC bit = “ ...
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... Analog output corresponding to digital input has group delay (GD). (3) If the soft mute is cancelled within the cycle set by the DVTM bit, the attenuation is discounted and returned to the value set by the DVL/R7-0 bits. MS0991-E-00 (Figure 49). D VTM bit ( (2) Figure 49. Soft Mute Function - VTM bit ( [AK4373] 2008/09 ...
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... Rin Figure 51. Block Diagram of Monaural input (Single Input) MS0991-E-00 noise.(Figure 51) DACH/S bit MINH/S bit − + 20k(typ) 20k(typ) 20k(typ) − + DACH/S bit MINH/S bit − + 20k(typ) 20k(typ) 20k(typ) − − Amp / SPK Amp − + − Amp / SPK Amp − + [AK4373] 2008/09 ...
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... HPG HPL/R PMHPL/R MINH DACH HPG - 59 - (Table 34). Available pins Figure Table Figure 1 Table 35 Figure 2 Table 36 Figure 3 Table 37 N/A Available pin / bit SPP/SPN PMSPK(SPPSN) MINS DACS SPKG[1:0] Available pin / bit HPR +/- PMHPR MINH DACH HPG Available pin / bit HVCM PMHPL or PMHPR - - - [AK4373] 2008/09 ...
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... Differential Pseudo cap-less HPL, HPR, HVCM Pseudo cap-less HPL, HPR, HVCM (1) (2) ( Table (Figure 52). Output pins Output Voltage [Vpp] HPL, HPR 0.6 x AVDD HPL, HPR 0.91 x AVDD HPL+/-, HPR+/- 1.2 x AVDD HPL+/-, HPR+/- 1.82 x AVDD 0.6 x AVDD 0.91 x AVDD N/A “1” (4) [AK4373] 38). When “0” 2008/09 ...
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... C [μF] fc [Hz] HVDD=2.7V AVDD=2.7V 220 45 20 100 100 100 149 100 50 5.0 47 106 220 45 44 (Note 100 100 22 62 0.9 10 137 - 61 - Table 39 shows the cut off Headphone 16Ω [mW]@0dBFS(Note 43) HVDD=3.3V HVDD=3.8V AVDD=3.3V AVDD=3. 7.5 7 44) (Note 44) 1.3 1.3 [AK4373] is 16Ω. L 2008/09 ...
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... Headphone-Amp is controlled by setting HTMTN bit. The common voltage is shown in 40. HPBTL bit should be changed when both speaker and headphone amps are powered-down. AK4373 Figure 54. External Circuit Example of Headphone (Differential output) MS0991-E-00 HPL+ pin HPL− pin HPR+ pin HPR− pin - Headphone Lch − + Headphone Rch − [AK4373] Table 2008/09 ...
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... VBAT bit Common Voltage [V] MS0991-E-00 40. PSEUDO bit should be changed when both speaker and headphone amps are HP-Amp HPL pin VCOM Amp for HP-Amp HVCM pin HP-Amp HPR pin 0 0.5 x HVDD Table 40. HP-Amp Common Voltage - 63 - Headphone R 16Ω 16Ω 0.64 x AVDD [AK4373] 2008/09 ...
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... Table 43. SPK-Amp Output Level - 64 - Piezo (Ceramic) Speaker 50Ω 3μF +6.43dB (default) +8.43dB ALC bit = “1” (LMTH1-0 bits = “00”) 3.11Vpp 45) 3.92Vpp 45) 6.37Vpp (Note 45) 45) 8.02Vpp (Note 45) 3.11Vpp 3.92Vpp 45) 6.37Vpp (Note 45) 45) 8.02Vpp (Note 45) [AK4373] 2008/09 ...
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... When a piezo speaker is used, two resistances more than 20Ω should be connected between SPP/SPN pins and speaker in series, respectively, as shown in Figure 56, in order to protect SPK-Amp of the AK4373 from the power that the piezo speaker outputs when the speaker is pressured. Zener diodes of the following zener voltage should be used. 0.92 x HVDD ≤ Zener voltage of zener diodo (ZD in Ex) In case of HVDD = 3.8V: 3.5V ≤ ...
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... Table 45. Speaker-Amp Mode Setting (x: Don’t care) PMSPK bit SPPSN bit SPP pin Hi-Z VSS2 HVDD/2 SPN pin VSS2 >1ms Figure 57. Power-up/Power-down Timing for Speaker-Amp MS0991-E-00 Mode SPP Power-down VSS2 Power-save Hi-Z Normal Operation Normal Operation - 66 - [AK4373] SPN VSS2 (default) HVDD/2 Normal Operation Hi-Z VSS2 HVDD/2 VSS2 >0 2008/09 ...
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... R/W “1” READ/WRITE (“1”: WRITE, “0”: READ); Fixed to “1” Register Address Control data Figure 58. Serial Control I/F Timing - Clock, “H” or “L” “H” or “L” [AK4373] 2008/09 ...
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... The AK4373 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4373 generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. After receiving each data packet the internal 6-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds 4FH prior to generating a stop condition, the address counter will “ ...
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... READ Operations Set the R/W bit = “1” for the READ operation of the AK4373. After transmission of data, the master can read the next address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word. After receiving each data packet the internal 6-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds 4FH prior to generating stop condition, the address counter will “ ...
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... MASTER S START CONDITION SDA SCL MS0991-E-00 S Figure 65. START and STOP Conditions 2 1 Figure 66. Acknowledge on the I data line change stable; of data data valid allowed Figure 67. Bit Transfer on the stop condition not acknowledge acknowledge 8 clock pulse for acknowledgement 2 C-Bus 2 C-Bus [AK4373] 9 2008/09 ...
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... F2A4 F2A3 F2A2 F2A1 F2A11 F2A10 F2A9 F2B4 F2B3 F2B2 F2B1 F2B11 F2B10 F2B9 [AK4373 PMPLL DIF0 FS0 RFST0 LMTH0 REF0 AVL0 DVL0 0 AVR0 DVR0 DEM0 DACH PFSEL F3A0 F3A8 F3B0 ...
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... E4C11 E4C10 E4C9 E5A3 E5A2 E5A1 E5A11 E5A10 E5A9 E5B3 E5B2 E5B1 E5B11 E5B10 E5B9 E5C3 E5C2 E5C1 E5C11 E5C10 E5C9 [AK4373] D0 EQ1 0 E1A0 E1A8 E1B0 E1B8 E1C0 E1C8 E2A0 E2A8 E2B0 E2B8 E2C0 E2C8 E3A0 E3A8 E3B0 E3B8 E3C0 E3C8 ...
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... For fully shut down (typ. 1μA), PDN pin must be “L”. When DAC is not used, external clocks may not be present. When DAC is used, external clocks must always be present. MS0991-E- PMVCM PMMIN PMSPK PMDAC [AK4373 2008/09 ...
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... Master Mode PMHPR: Headphone-Amp Rch Power Management 0: Power-down (default) 1: Power-up PMHPL: Headphone-Amp Lch Power Management 0: Power-down (default) 1: Power-up HPMTN: Headphone-Amp Mute Control 0: Mute (default) 1: Normal operation MS0991-E- HPMTN PMHPL PMHPR M/S MCKAC MCKO [AK4373] D0 PMPLL 0 2008/09 ...
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... PLL2 PLL1 (Table 17) (Table 11) (Table HPBTL 0 PSEUDO Figure Table Figure 1 Table 35 Figure 2 Table 36 Figure 3 Table 37 N SPKG0 PLL0 BCKO DIF2 DIF1 [AK4373 DIF0 0 2008/09 ...
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... The rising edge (“↑”) of LRCK is one clock of BICK before the channel change. PS1-0: MCKO Output Frequency Select Default: “00” (256fs) MS0991-E- PS1 PS0 FS3 MSBS (Table 6 and Table 7.) and MCKI Frequency Select (Table 18) (Table 18) (Table 10 [AK4373 BCKP FS2 FS1 FS0 (Table 12.) 2008/09 ...
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... REF7 REF6 REF5 REF4 WTM1 WTM0 RFST1 (Table 24 LMAT1 LMAT0 RGAIN0 (Table 22 REF3 REF2 REF1 (Table 27.) [AK4373] D0 RFST0 0 D0 LMTH0 0 D0 REF0 1 2008/09 ...
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... AVL1 AVR3 AVR2 AVR1 (Table 30 DVL3 DVL2 DVL1 DVR3 DVR2 DVR1 FRN VBAT (Table 22 DEM1 [AK4373] D0 AVL0 AVR0 1 D0 DVL0 DVR0 DEM0 1 2008/09 ...
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... HPG (Table 38 GN1 GN0 LPF AVOLC HPM MINH HPF EQ FIL3 [AK4373] D0 DACH 2008/09 ...
Page 80
... LPF: Low pass filter Coefficient Setting Enable 0: Disable (default) 1: Enable When LPF bit is “1”, the settings of F2A13-0 and F2B13-0 bits are valid. When LPF bit is “0”, LPF block is through (0dB). GN1-0: Gain Select at GAIN block Default: “00” MS0991-E-00 (Table 21 [AK4373] 2008/09 ...
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... F1A9 F1B3 F1B2 F1B1 F1B11 F1B10 F1B9 F2A3 F2A2 F2A1 F2A11 F2A10 F2A9 F2B3 F2B2 F2B1 F2B11 F2B10 F2B9 [AK4373] D0 F3A0 F3A8 F3B0 F3B8 EQA0 EQA8 EQB0 EQB8 EQC0 EQC8 F1A0 F1A8 F1B0 F1B8 F2A0 F2A8 F2B0 F2B8 0 2008/09 ...
Page 82
... When EQ5 bit is “1”, the settings of E5A15-0, E5B15-0 and E5C15-0 bits are enabled. When EQ5 bit is “0”, EQ5 block is through (0dB). MS0991-E- EQ5 R [AK4373 EQ4 EQ3 EQ2 EQ1 R/W R/W R/W R 2008/09 ...
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... E5A1 E5A11 E5A10 E5A9 E5B3 E5B2 E5B1 E5B11 E5B10 E5B9 E5C3 E5C2 E5C1 E5C11 E5C10 E5C9 [AK4373] D0 E1A0 E1A8 E1B0 E1B8 E1C0 E1C8 E2A0 E2A8 E2B0 E2B8 E2C0 E2C8 E3A0 E3A8 E3B0 E3B8 E3C0 E3C8 E4A0 E4A8 E4B0 ...
Page 84
... All digital input pins should not be left floating. - When the AK4373 is EXT mode (PMPLL bit = “0”), a resistor and a capacitor of the VCOC pin are not needed. - When the AK4373 is PLL mode (PMPLL bit = “1”), a resistor and a capacitor of the VCOC pin are shown in Table 5 ...
Page 85
... All digital input pins must not be left floating. - When the AK4373 is EXT mode (PMPLL bit = “0”), a resistor and a capacitor of the VCOC pin are not needed. - When the AK4373 is PLL mode (PMPLL bit = “1”), a resistor and a capacitor of the VCOC pin are shown in Table 5 ...
Page 86
... All digital input pins must not be left floating. - When the AK4373 is EXT mode (PMPLL bit = “0”), a resistor and a capacitor of the VCOC pin are not needed. - When the AK4373 is PLL mode (PMPLL bit = “1”), a resistor and a capacitor of the VCOC pin are shown in Table 5 ...
Page 87
... If AVDD, DVDD and HVDD are supplied separately, the power-up sequence is not critical. VSS1, VSS2 and VSS3 of the AK4373 must be connected to the analog ground plane. System analog ground and digital ground must be connected together near to where the supplies are brought onto the printed circuit board ...
Page 88
... PLL lock time is 40ms(max) after PMPLL bit changes from “0” to “1” and MCKI is supplied from an external source. (6) The AK4373 starts to output the LRCK and the BICK clocks after the PLL becomes stable. Then normal operation starts. (7) The invalid frequency is output from the MCKO pin during this period if MCKO bit = “1”. ...
Page 89
... Internal Clock <Example> (2) After Power Up: PDN pin “L” “L” time of 150ns or more is needed to reset the AK4373. (3) DIF1-0, FS3-0 and PLL3-0 bits should be set during this period. (4) Power Up VCOM: PMVCM bit = “0” VCOM must first be powered up before the other block operates. ...
Page 90
... LRCK pin <Example> (1) After Power Up: PDN pin “L” “L” time of 150ns or more is needed to reset the AK4373. (2) DIF1-0, PLL3-0 and FS3-0 bits should be set during this period. (3) Power Up VCOM: PMVCM bit = “0” VCOM must first be powered up before the other block operates. ...
Page 91
... BICK pin <Example> (1) After Power Up: PDN pin “L” “L” time of 150ns or more is needed to reset the AK4373. (2) DIF1-0 and FS1-0 bits must be set during this period. (3) Power Up VCOM: PMVCM bit = “0” VCOM must first be powered up before the other block operates. ...
Page 92
... BICK pin <Example> (1) After Power Up: PDN pin “L” “L” time of 150ns or more is needed to reset the AK4373. (2) MCKI must be input. (3) After DIF1-0 and FS1-0 bits are set, M/S bit should be set to “1”. Then LRCK and BICK are output. (4) Power Up VCOM: PMVCM bit = “0” ...
Page 93
... SPN pin <Example> At first, clocks should be supplied according to “Clock Set Up” sequence. (1) Set up a sampling frequency (FS3-0 bits). When the AK4373 is PLL mode, DAC and Speaker-Amp should be powered-up in consideration of PLL lock time after a sampling frequency is changed. (2) Set up the path of “DAC (3) SPK-Amp gain setting: SPKG1-0 bits = “00” ...
Page 94
... At first, clocks should be supplied according to “Clock Set Up” sequence. (1) Set up a sampling frequency (FS3-0 bits). When the AK4373 is PLL mode, DAC and Speaker-Amp should be powered-up in consideration of PLL lock time after a sampling frequency is changed. (2) Set up the path of “DAC → HP-Amp”: DACH bit = “0” → “1” ...
Page 95
... Stop an external MCKI Example Audio I/F Format : MSB justified PLL Reference clock: BICK BICK frequency: 64fs (1) Addr:01H, Data:00H (2) Stop the external clocks Example Audio I/F Format: MSB justified PLL Reference clock: MCKI BICK frequency: 64fs (1) Addr:01H, Data:00H (2) Stop the external clocks [AK4373] 2008/09 ...
Page 96
... Figure 81. Clock Stopping Sequence (4) "H" or "L" "H" or "L" Figure 82. Clock Stopping Sequence ( Example Audio I/F Format :MSB justified Input MCKI frequency:1024fs (1) Stop the external clocks Example Audio I/F Format :MSB justified Input MCKI frequency:1024fs (1) Stop the external MCKI [AK4373] 2008/09 ...
Page 97
... Note) The exposed pad on the bottom surface of the package must be open or connected to the ground. ■ Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: MS0991-E-00 PACKAGE 0.40 ± 0. C0. Epoxy Cu Solder (Pb free) plate - 97 - [AK4373] Exposed Pad 32 1 3.5 2008/09 ...
Page 98
... MS0991-E-00 MARKING AKM AK4373 XXXXX 1 XXXXX : Date code identifier (5 digits) REVISION HISTORY Reason Page Contents First Edition IMPORTANT NOTICE , and AKEMD assumes no responsibility for such use, except for the use Note2 [AK4373] in any safety, life support, or Note1) 2008/09 ...