ak4373 ETC-unknow, ak4373 Datasheet - Page 35

• Manufacturer Part Number: ak4373
• Description: Low Power Stereo Dac With Hp/spk-amp
• Manufacturer: ETC-unknow

■
When PMPLL bit is “0”, the AK4373 changes to EXT mode. Master clock is input from the MCKI pin, the internal PLL
circuit is not operated. This mode is compatible with I/F of a normal audio DAC. The clocks required to operate are MCKI
(256fs, 512fs or 1024fs), LRCK (fs) and BICK (≥32fs). The master clock (MCKI) should be synchronized with LRCK.
The phase between these clocks is not important. The input frequency of MCKI is selected by FS1-0 bits
The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise.
The out-of-band noise can be improved by using higher frequency of the master clock. The S/N of the DAC output
through HPL/HPR pins at fs=8kHz is shown in
The external clocks (MCKI, BICK and LRCK) should always be present whenever the DAC is in operation (PMDAC bit
= “1”). If these clocks are not provided, the AK4373 may draw excess current and it is not possible to operate properly
because utilizes dynamic refreshed logic internally. If the external clocks are not present, the DAC must be in the
power-down mode (PMDAC bit = “0”).
MS0991-E-00
EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
Mode
0
1
2
3
FS3-2 bits
Table 12. MCKI Frequency at EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”) (x: Don’t care)
x
x
x
x
Table 13. Relationship between MCKI and S/N of HPL/HPR pins
Mode
AK4373
0
2
3
1
FS1 bit
0
0
1
1
MCKO
MCKI
BICK
LRCK
SDTI
1024fs
MCKI
256fs
512fs
512fs
Figure 28. EXT Slave Mode
Table
FS0 bit
256fs, 512fs or 1024fs
0
1
0
1
(fs=8kHz, 20kHzLPF + A-weighted)
13.
- 35 -
≥ 32fs
1fs
MCKI Input
Frequency
1024fs
256fs
512fs
512fs
56dB
75dB
93dB
S/N
MCLK
BCLK
LRCK
SDTO
DSP or μP
Sampling Frequency
7.35kHz ∼ 48kHz
7.35kHz ∼ 13kHz
7.35kHz ∼ 26kHz
7.35kHz ∼ 48kHz
Range
(default)
(Table
[AK4373]
2008/09
12).