ak4373 ETC-unknow, ak4373 Datasheet - Page 53

• Manufacturer Part Number: ak4373
• Description: Low Power Stereo Dac With Hp/spk-amp
• Manufacturer: ETC-unknow

3. Example of ALC Operation
Table 29
The following registers should not be changed during ALC operation. These bits should be changed after ALC operation
is finished by ALC bit = “0” or PMDAC bit = “0”.
MS0991-E-00
Register Name
LMTH1-0
ZELMN
ZTM1-0
WTM2-0
REF7-0
AVL7-0,
AVR7-0
LMAT1-0
RGAIN1-0
RFST1-0
ALC
• LMTH1-0, LMAT1-0, WTM2-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMN, RFST1-0
shows the examples of the ALC setting.
WR (LMAT1-0, RGAIN0, ZELMN, LMTH0; ALC= “1”)
WR (ZTM1-0, WTM2-0, RFST1-0)
Comment
Limiter detection Level
Limiter zero crossing detection
Zero crossing timeout period
Recovery waiting period
*WTM2-0 bits should be the same or
Maximum gain at recovery operation
Gain of AVOL
Limiter ATT step
Recovery GAIN step
Fast Recovery Speed
ALC enable
WR (RGAIN1, LMTH1)
longer data as ZTM1-0 bits.
Note : WR : Write
WR (AVL/R7-0)
ALC Operation
Manual Mode
WR (REF7-0)
Figure 47. Registers set-up sequence at ALC operation
Table 29. Example of the ALC setting
* The value of AVOL should be
the same or smaller than REF’s
- 53 -
Data
E1H
E1H
001
01
01
00
00
00
0
1
fs=8kHz
Example:
−4.1dBFS
Operation
4 times
Enable
Enable
+30dB
+30dB
1 step
1 step
32ms
32ms
Limiter = Zero crossing Enable
Recovery Cycle = 32ms@8kHz
Limiter and Recovery Step = 1
Maximum Gain = +30.0dB
Limiter Detection Level = −4.1dBFS
ALC bit = “1”
(3) Addr=09H&0CH, Data=E1H
(1) Addr=06H, Data=14H
(2) Addr=08H, Data=E1H
(4) Addr=0BH, Data=00H
(5) Addr=07H, Data=01H
Data
E1H
E1H
011
01
11
00
00
00
0
1
fs=44.1kHz
−4.1dBFS
Operation
23.2ms
23.2ms
4 times
Enable
Enable
+30dB
+30dB
1 step
1 step
[AK4373]
2008/09