ak4373 ETC-unknow, ak4373 Datasheet - Page 50

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ak4373

Manufacturer Part Number
ak4373
Description
Low Power Stereo Dac With Hp/spk-amp
Manufacturer
ETC-unknow
Datasheet

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Part Number:
ak4373EN-L
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Quantity:
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The ALC (Automatic Level Control) is controlled by ALC block when ALC bit is “1”.
1. ALC Limiter Operation
During ALC limiter operation, when either Lch or Rch exceeds the ALC limiter detection level
AVR values (same value) are attenuated automatically by the amount defined by the ALC limiter ATT step
When ZELMN bit = “0” (zero cross detection is enabled), the AVL and AVR values are changed by ALC limiter
operation at the individual zero crossing points of Lch and Rch or at the zero crossing timeout. ZTM1-0 bits set the zero
crossing timeout period of both ALC limiter and recovery operation
full-scale, IVL and IVR values are immediately (Period: 1/fs) changed. When ALC output level is less than full-scale,
IVL and IVR values are changed at the individual zero crossing point of each channels or at the zero crossing timeout.
When ZELMN bit = “1” (zero cross detection is disabled), AVL and AVR values are immediately (period: 1/fs) changed
by ALC limiter operation. Attenuation step is fixed to 1 step regardless of the setting of LMAT1-0 bits.
The attenuate operation is done continuously until the input signal level becomes ALC limiter detection level
or less. After completing the attenuate operation, unless ALC bit is changed to “0”, the operation repeats when the input
signal level exceeds LMTH1-0 bits.
MS0991-E-00
ALC Operation
LMTH1
0
0
1
1
ZTM1
LMTH0
0
0
1
1
0
1
0
1
LMAT1
Table 22. ALC Limiter Detection Level / Recovery Counter Reset Level
0
0
1
1
ZTM0
ALC Limier Detection Level
ALC Output ≥ −2.5dBFS
ALC Output ≥ −4.1dBFS
ALC Output ≥ −6.0dBFS
ALC Output ≥ −8.5dBFS
0
1
0
1
LMAT0
Table 24. ALC Zero Crossing Timeout Period
0
1
0
1
1024/fs
128/fs
256/fs
512/fs
Table 23. ALC Limiter ATT Step
ALC1 Limiter ATT Step (0.375dB/step)
128ms
8kHz
16ms
32ms
64ms
ALC1 Output ≥ LMTH
- 50 -
Zero Crossing Timeout Period
ALC Recovery Waiting Counter Reset Level
−2.5dBFS > ALC Output ≥ −4.1dBFS
−4.1dBFS > ALC Output ≥ −6.0dBFS
−6.0dBFS > ALC Output ≥ −8.5dBFS
−8.5dBFS > ALC Output ≥ −12dBFS
1
2
2
1
(Table
16kHz
16ms
32ms
64ms
8ms
24). When ALC output level exceeds
44.1kHz
23.2ms
11.6ms
2.9ms
5.8ms
(default)
(Table
(default)
22), the AVL and
(default)
(Table
(Table
[AK4373]
2008/09
23).
22)

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