ak4319a AKM Semiconductor, Inc., ak4319a Datasheet
ak4319a
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ak4319a Summary of contents
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... ASAHI KASEI The AK4319A is a high performance 1bit stereo DAC for digital audio systems. A 1bit DAC can achieve monotonicity and low distortion with no adjustment. On chip SCF filter makes the device less affected to the clock jitter and also suppresses the undesirable radio emission noise. The device equips differentially configurated output pins, but either of the pins can be used as single-end ...
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... ASAHI KASEI Ordering Guide AK4319AVM AKD4319A Pin Layout Different Points from AK4319 Parameter fs(min) THD+N DR S/N M0011-E-01 -40 +85 C 24pin SSOP(0.65mm pitch) Evaluation Board AK4319 AK4319A 10kHz 8kHz -90dB -87dB 96dB 92dB 96dB 92dB - 2 - [AK4319A] 1998/6 ...
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... Audio Serial Data Input Pin 2's complement MSB-first data is input on this pin Power-Down Mode Pin When at "L", the AK4319A is in power-down mode and is held in reset. The AK4319A should always be reset upon power-up. 8 XTI I Master Clock Input Pin A crystal can be connected between this pin and XTO external CMOS clock can be input on XTI ...
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... Notes:2 . AVDD and DVDD should be powered at the same time or AVDD should be powered earlier than DVDD. * AKM assumes no responsibility for the usage beyond the conditions in this data sheet. M0011-E-01 ABSOLUTE MAXIMUM RATINGS Symbol AVDD DVDD VDA IIN VIND Ta Tstg Symbol min AVDD 4.5 DVDD 4 [AK4319A] min max Units -0.3 6.0 V -0 ±10 -0.3 AVDD+0.3 V -40 ...
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... M0011-E-01 ANALOG CHARACTERISTICS 5k ; unless otherwise specified) L min typ (Note 100 0.15 100 (Note 4 ) ±2.60 ±2. (Note (Note (Note [AK4319A] max Units 18 Bits - 0 ppm/ C Vpp ±3.00 k 300 135 1998/6 ...
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... DIGITAL CHARACTERISTICS Symbol min (XTI pin) VIH1 70%DVDD VIH2 2.2 (XTI pin) VIL1 - VIL2 - (XTI pin) VAC 1 (Iout=-100uA) VOH DVDD-0.5 (Iout=100uA) VOL - (Note 9 ) Iin - - 6 - [AK4319A] typ max Units 20.0 kHz 22.05 - kHz kHz dB ±0.06 dB 14 ±0.2 typ max Units - - 30%DVDD V - ...
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... SDATA Hold Time SDATA Setup Time Reset Timing PD Pulse Width (Note 11 ) Notes: 10. BICK rising edge must not occur at the same time as LRCK edge. 11. The AK4319A can be reset by bringing PD "L" to "H" only upon power up. M0011-E-01 SWITCHING CHARACTERISTICS =20pF) L Symbol min fCLK 7 ...
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... ASAHI KASEI Timing Diagram M0011-E-01 Reset Timing - 8 - [AK4319A] 1998/6 ...
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... The AK4319A should be reset by provided. If the external clocks are not present, the AK4319A should be in the power-down mode( After exiting reset at power-up etc., the AK4319A is in power-down mode until XTI and LRCK are input. LRCK (fs) ...
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... LSB Justified 18bit LSB Justified 18bit MSB Justified M0011-E-01 Mode BICK 32fs 36fs 36fs 2 S Compatible 36fs or 32fs Table 2 . Serial Data Modes Figure 3 . Mode 0,1 Timing Figure 4 . Mode 2 Timing Figure 5 . Mode 3 Timing - 10 - [AK4319A] Figure Figure 2 Figure 2 Figure 3 Figure 4 1998/6 ...
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... ASAHI KASEI De-emphasis filter The AK4319A includes the digital de-emphasis filter(tc=50/15us) by IIR filter. This filter corresponds to three sampling frequencies(32kHz,44.1kHz,48kHz). De-emphasis is enabled by the following two ways. Zero detection After the input data at both channels are continuously zeros for 8192 LRCK cycles or when the muting period exceeds 8192+1022 LRCK cycles, DZF goes to " ...
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... ASAHI KASEI Power-Down The AK4319A are placed in the power-down mode by bringing PD pin "L" and the analog outputs are floating(Hi-Z). Figure 7 shows an example of the system timing at the power-down and power-up. Analog output has the group delay(GD When power-down is initiated, analog outputs are set into Hi-Z. Output noise level is about -110dB. Some -50dB of click noise occurs at the transition(" ...
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... AVDD should be powered earlier than DVDD. Analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors for high frequency should be placed as near as possible. M0011-E-01 SYSTEM DESIGN - 13 - [AK4319A] 1998/6 ...
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... Especially, the ceramic capacitor should be connected to VREF pin within a few mm as near as possible. No load current may be taken from the VREF output pin. All signals, especially clocks, should be kept away from the VREF pin in order to avoid unwanted coupling into the AK4319A. 3. Analog Outputs The analog signals are output from the differential output pins of each channel, therefore they are summed externally ...
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... ASAHI KASEI 4. Single-end usage The load impedance for the output pin should be higher than 5k . When the AK4319A drives some capacitive load, series resistor(220ohm or more than) should be added the analog output and it should be connected to the analog output pin as near as possible. The output pin which is not used could be left open. When the AK4319A is used as a single-end configuration, the analog characteristics (such as THD+N, DR, S/N) may degrade by 1dB ...
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... ASAHI KASEI 24pin SSOP (Unit: mm) NOTE: Dimension “*” does not include mold flash. Package & Lead frame material Package molding compound: Lead frame material: Lead frame surface treatment: M0011-E-01 PACKAGE Epoxy Cu Solder plate - 16 - [AK4319A] 1998/6 ...
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... ASAHI KASEI M0011-E-01 MARKING Contents of AAXXXX AA: Lot# XXXX: Date Code - 17 - [AK4319A] 1998/6 ...
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IMPORTANT NOTICE These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. AKM assumes no liability ...