xr16v2651im Exar Corporation, xr16v2651im Datasheet - Page 10

• Manufacturer Part Number: xr16v2651im
• Description: High Performance Duart With 32-byte Fifo And Powersave
• Manufacturer: Exar Corporation

XR16V2651
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE
The device does not support direct memory access. The DMA Mode (a legacy term) in this document doesn’t
mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of
the RXRDY# A/B and TXRDY# A/B output pins. The transmit and receive FIFO trigger levels provide additional
flexibility to the user for block mode operation. The LSR bits 5-6 provide an indication when the transmitter is
empty or has an empty location(s) for more data. The user can optionally operate the transmit and receive
FIFO in the DMA mode (FCR bit-3=1). When the transmit and receive FIFO are enabled and the DMA mode is
disabled (FCR bit-3 = 0), the V2651 is placed in single-character mode for data transmit or receive operation.
When DMA mode is enabled (FCR bit-3 = 1), the user takes advantage of block mode operation by loading or
unloading the FIFO in a block sequence determined by the selected trigger level. In this mode, the V2651 sets
the TXRDY# pin when the transmit FIFO becomes full, and sets the RXRDY# pin when the receive FIFO
becomes empty. The following table shows their behavior. Also see
The INTA and INTB interrupt output changes according to the operating mode and enhanced features setup.
Table 4 and 5
through
2.6
2.7
RXRDY# A/B LOW = 1 byte
TXRDY# A/B LOW = THR empty
INTA/B Pin
INTA/B Pin
P
INS
DMA Mode
INTA and INTB Outputs
24.
HIGH = no data
HIGH = byte in THR
summarize the operating behavior for the transmitter and receiver. Also see
(FIFO D
LOW = a byte in THR
HIGH = THR empty
LOW = no data
HIGH = 1 byte
FCR
T
ABLE
BIT
ISABLED
T
-0=0
ABLE
T
3: TXRDY#
ABLE
)
4: INTA
(FIFO D
(FIFO D
FCR B
FCR B
5: INTA
LOW = at least 1 byte in FIFO
HIGH = FIFO empty
LOW = FIFO empty
HIGH = at least 1 byte in FIFO
(DMA Mode Disabled)
AND
IT
ISABLED
IT
ISABLED
AND
-0 = 0
-0 = 0
AND
FCR Bit-3 = 0
INTB P
RXRDY# O
INTB P
)
)
INS
10
IN
O
UTPUTS IN
O
PERATION FOR
PERATION
FCR B
LOW = FIFO above trigger level
HIGH = FIFO below trigger level or FIFO empty
LOW = FIFO below trigger level
HIGH = FIFO above trigger level
IT
HIGH to LOW transition when FIFO reaches the
trigger level, or time-out occurs
LOW to HIGH transition when FIFO empties
LOW = FIFO has at least 1 empty location
HIGH = FIFO is full
-0=1 (FIFO E
FIFO
Figures 19
F
OR
T
AND
FCR B
RANSMITTER
R
ECEIVER
DMA M
(DMA Mode Enabled)
NABLED
IT
(FIFO E
through 24.
-0 = 1 (FIFO E
FCR B
FCR Bit-3 = 1
ODE
)
IT
NABLED
-0 = 1
NABLED
)
Figures 19
)
REV. 1.0.2