xr16v2651im Exar Corporation, xr16v2651im Datasheet - Page 29

• Manufacturer Part Number: xr16v2651im
• Description: High Performance Duart With 32-byte Fifo And Powersave
• Manufacturer: Exar Corporation

REV. 1.0.2
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
•
•
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
•
•
FCR[3]: DMA Mode Select
Controls the behavior of the TXRDY# and RXRDY# pins. See DMA operation section for details.
•
•
FCR[5:4]: Transmit FIFO Trigger Select (requires EFR bit-4=1)
(logic 0 = default, TX trigger level = 1)
These 2 bits set the trigger level for the transmit FIFO. The UART will issue a transmit interrupt when the
number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that the
FIFO did not get filled over the trigger level on last re-load.
must be set to ‘1’ before these bits can be accessed.
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
the number of the characters in the FIFO crosses the trigger level.
Whichever selection is made last applies to both the RX and TX side.
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
4.6
Logic 0 = No receive FIFO reset (default)
Logic 1 = Reset the receive FIFO pointers (the receive shift register is not cleared or altered). This bit will
return to a logic 0 after resetting the FIFO.
Logic 0 = No transmit FIFO reset (default).
Logic 1 = Reset the transmit FIFO pointers (the transmit shift register is not cleared or altered). This bit will
return to a logic 0 after resetting the FIFO.
Logic 0 = Normal Operation (default).
Logic 1 = DMA Mode.
Line Control Register (LCR) - Read/Write
T
ABLE
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE
12: T
B
FCR
IT
0
0
1
1
RANSMIT AND
-7
B
FCR
IT
0
1
0
1
-6
R
B
FCR
ECEIVE
IT
0
0
1
1
-5
BIT
FCR
FIFO T
0
1
0
1
-4
29
T
RIGGER
RIGGER
R
Table 12
ECEIVE
16
24
28
8
T
L
ABLE AND
EVEL
Table 12
below shows the selections. EFR bit-4
T
T
RANSMIT
L
RIGGER
L
EVEL
EVEL
16
24
30
shows the complete selections.
8
S
ELECTION
XR16V2651