xr16v2651im Exar Corporation, xr16v2651im Datasheet - Page 9

• Manufacturer Part Number: xr16v2651im
• Description: High Performance Duart With 32-byte Fifo And Powersave
• Manufacturer: Exar Corporation

REV. 1.0.2
The RESET input resets the internal registers and the serial interface outputs in both channels to their default
state (see
function in the device.
The XR16V2651 provides a Device Identification code and a Device Revision code to distinguish the part from
other devices and revisions. To read the identification code from the part, it is required to set the baud rate
generator registers DLL and DLM both to 0x00 (DLD = 0xXX). Now reading the content of the DVID will
provide 0x06 for the XR16V2651 and reading the content of DREV will provide the revision of the part; for
example, a reading of 0x01 means revision A.
The UART provides the user with the capability to bi-directionally transfer information between an external
CPU and an external serial communication device. During Intel Bus Mode (16/68# pin connected to VCC), a
logic 0 on chip select pins, CSA# or CSB#, allows the user to select UART channel A or B to configure, send
transmit data and/or unload receive data to/from the UART. Selecting both UARTs can be useful during power
up initialization to write to the same internal registers, but do not attempt to read from both UARTs
simultaneously. Individual channel select functions are shown in
During Motorola Bus Mode (16/68# pin connected to GND), the package interface pins are configured for
connection with Motorola, and other popular microprocessor bus types. In this mode the V2651 decodes an
additional address, A3, to select one of the UART ports. The A3 address decode function is used only when in
the Motorola Bus Mode.
Each UART channel in the V2651 has a set of enhanced registers for control, monitoring and data loading and
unloading. The configuration register set is compatible to those already available in the standard single
16C550 and dual ST16C2550. These registers function as data holding registers (THR/RHR), interrupt status
and control registers (ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/
LCR), modem status and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/
DLM/DLD), and a user accessible Scratchpad Register (SPR).
Beyond the general 16C2550 features and capabilities, the V2651 offers enhanced feature registers (EFR,
Xon/Xoff 1, Xon/Xoff 2) that provide automatic RTS and CTS hardware flow control, and Xon/Xoff software flow
control. All the register functions are discussed in full detail later in
REGISTERS” on page
2.3
2.4
2.5
Device Reset
Device Identification and Revision
Channel A and B Selection
Table
16). An active high pulse of longer than 40 ns duration will be required to activate the reset
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE
23.
See Table
T
T
CSA#
ABLE
ABLE
CS#
1
0
1
0
1
0
0
2.
1: C
2: C
HANNEL
HANNEL
CSB#
N/A
A3
1
1
0
0
0
1
A
A
AND
AND
9
Channel A and B selected
B S
B S
Channel A selected
Channel B selected
Channel A selected
Channel B selected
UART de-selected
UART de-selected
ELECT IN
ELECT IN
F
F
UNCTION
UNCTION
Table
16 M
68 M
1.
ODE
ODE
“Section 3.0, UART INTERNAL
XR16V2651