sc16is760ipw NXP Semiconductors, sc16is760ipw Datasheet
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sc16is760ipw Summary of contents
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SC16IS740/750/760 Single UART with I and receive FIFOs, IrDA SIR built-in support Rev. 05 — 16 November 2006 1. General description The SC16IS740/750/760 is a slave I performance UART. It offers data rates Mbit/s and guarantees low ...
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... NXP Semiconductors eight programmable I/O pins (SC16IS750 and SC16IS760 only) I RS-485 driver direction control via RTS signal I RS-485 driver direction control inversion I Built-in IrDA encoder and decoder interface I SC16IS750 supports IrDA SIR with speeds up to 115.2 kbit/s I SC16IS760 supports IrDA SIR with speeds up to 1.152 Mbit/s ...
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... Package Name SC16IS740IPW TSSOP16 SC16IS750IBS HVQFN24 SC16IS750IPW TSSOP24 SC16IS760IBS HVQFN24 SC16IS760IPW TSSOP24 SC16IS740_750_760_5 Product data sheet Single UART with I Description plastic thin shrink small outline package; 16 leads; body width 4.4 mm plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 4 0.85 mm plastic thin shrink small outline package ...
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... NXP Semiconductors 5. Block diagram Fig 1. Block diagram of SC16IS750/760 I Fig 2. Block diagram of SC16IS740 I SC16IS740_750_760_5 Product data sheet 2 Single UART with I C-bus/SPI interface, 64-byte FIFOs, IrDA SIR SC16IS750/760 RESET SCL SDA C-BUS A1 IRQ 1 k (3.3 V) 1 I2C/SPI XTAL1 XTAL2 2 C-bus interface ...
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... NXP Semiconductors Fig 3. Block diagram of SC16IS750/760 SPI interface Fig 4. Block diagram of SC16IS740 SPI interface SC16IS740_750_760_5 Product data sheet 2 Single UART with I C-bus/SPI interface, 64-byte FIFOs, IrDA SIR SC16IS750/760 RESET SCLK CS SO SPI SI IRQ 1 k (3.3 V) 1 I2C/SPI XTAL1 XTAL2 SC16IS740 RESET ...
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... IRQ 7 10 RTS 8 9 SPI V 002aab974 1 24 RTS 2 23 GPIO7/ GPIO6/ GPIO5/DTR 5 20 GPIO4/DSR SC16IS750IPW 7 18 GPIO3 SC16IS760IPW 8 17 GPIO2 9 16 GPIO1 GPIO0 11 14 IRQ 002aab399 © NXP B.V. 2006. All rights reserved ...
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... NXP Semiconductors terminal 1 index area 1 RESET XTAL1 2 XTAL2 3 SC16IS750IBS SC16IS760IBS I2C Transparent top view C-bus interface Fig 7. Pin configuration for HVQFN24 6.2 Pin description Table 2. Pin description Symbol Pin TSSOP16 TSSOP24 HVQFN24 CTS RESET ...
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... NXP Semiconductors Table 2. Pin description …continued Symbol Pin TSSOP16 TSSOP24 HVQFN24 CS/ SI/ SCL/SCLK 5 12 SDA 6 13 IRQ 7 14 GPIO0 - 15 GPIO1 - 16 GPIO2 - 17 GPIO3 - 18 GPIO4/DSR - 20 GPIO5/DTR - 21 GPIO6/ GPIO7/ RTS [1] See Section 7.4 “Hardware reset, Power-On Reset (POR) and software reset” ...
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... NXP Semiconductors [3] HVQFN package die supply ground is connected to both V ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the PCB in the thermal pad region ...
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... NXP Semiconductors Fig 8. Autoflow control (auto RTS and auto CTS) example 7.2.1 Auto RTS Figure 9 are stored in the TCR or FCR. RTS is active if the RX FIFO level is below the halt trigger level in TCR[3:0]. When the receiver FIFO halt trigger level is reached, RTS is deasserted. ...
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... NXP Semiconductors 7.2.2 Auto CTS Figure 10 sending the next data byte. When CTS is active, the transmitter sends the next byte. To stop the transmitter from sending the following byte, CTS must be deasserted before the middle of the last stop bit that is currently being sent. The auto CTS function reduces interrupts to the host system. When fl ...
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... NXP Semiconductors There are two other enhanced features relating to software flow control: • Xon Any function (MCR[5]): Receiving any character will resume operation after recognizing the Xoff character possible that an Xon1 character is recognized as an Xon Any character, which could cause an Xon2 character to be written to the RX FIFO. • ...
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... NXP Semiconductors Fig 11. Example of software flow control SC16IS740_750_760_5 Product data sheet 2 Single UART with I C-bus/SPI interface, 64-byte FIFOs, IrDA SIR UART1 TRANSMIT FIFO data PARALLEL-TO-SERIAL Xoff–Xon–Xoff SERIAL-TO-PARALLEL Xon1 WORD Xon2 WORD Xoff1 WORD compare Xoff2 WORD programmed ...
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... NXP Semiconductors 7.4 Hardware reset, Power-On Reset (POR) and software reset These three reset methods are identical and will reset the internal registers as indicated in Table 4. Table 4 Table 4. Register Interrupt Enable Register Interrupt Identification Register FIFO Control Register Line Control Register Modem Control Register ...
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... NXP Semiconductors 7.5 Interrupts The SC16IS740/750/760 has interrupt generation and prioritization (seven prioritized levels of interrupts) capability. The interrupt enable registers (IER and IOIntEna) enable each of the seven types of interrupts and the IRQ signal in response to an interrupt generation. When an interrupt is generated, the IIR indicates that an interrupt is pending and provides the type of interrupt through IIR[5:0] ...
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... NXP Semiconductors 7.5.1 Interrupt mode operation In Interrupt mode (if any bit of IER[3: the host is informed of the status of the receiver and transmitter by an interrupt signal, IRQ. Therefore not necessary to continuously poll the Line Status Register (LSR) to see if any interrupt needs to be serviced. ...
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... NXP Semiconductors 7.6 Sleep mode Sleep mode is an enhanced feature of the SC16IS740/750/760 UART enabled when EFR[4], the enhanced functions bit, is set and when IER[4] is set. Sleep mode is entered when: • The serial data input line, RX, is idle (see conditions”). • ...
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... NXP Semiconductors Figure 14 XTAL1 XTAL2 Fig 14. Prescaler and baud rate generator block diagram DLL and DLH must be written to in order to program the baud rate. DLL and DLH are the least significant and most significant byte of the baud rate divisor. If DLL and DLH are both zero, the UART is effectively disabled baud clock will be generated ...
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... NXP Semiconductors Table 8. Desired baud rate 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 Fig 15. Crystal oscillator circuit reference SC16IS740_750_760_5 Product data sheet 2 Single UART with I Baud rates using a 3.072 MHz crystal Divisor used to generate ...
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... NXP Semiconductors 8. Register descriptions The programming combinations for register selection are shown in Table 9. Register name Read mode RHR/THR IER IIR/FCR LCR MCR LSR MSR SPR TCR TLR TXLVL RXLVL [3] IODir IOState IOIntEna IOControl EFCR DLL DLH EFR XON1 XON2 XOFF1 XOFF2 [1] MCR[7] can only be modifi ...
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Table 10. SC16IS740/750/760 internal registers Register Register Bit 7 Bit 6 address [1] General register set 0x00 RHR bit 7 bit 6 0x00 THR bit 7 bit 6 0x01 IER CTS RTS interrupt [2] interrupt enable [2] enable 0x02 FCR ...
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Table 10. SC16IS740/750/760 internal registers Register Register Bit 7 Bit 6 address [9] Special register set 0x00 DLL bit 7 bit 6 0x01 DLH bit 7 bit 6 [10] Enhanced register set 0x02 EFR Auto CTS Auto RTS 0x04 XON1 ...
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... NXP Semiconductors 8.1 Receive Holding Register (RHR) The receiver section consists of the Receiver Holding Register (RHR) and the Receiver Shift Register (RSR). The RHR is actually a 64-byte FIFO. The RSR receives serial data from the RX pin. The data is converted to parallel data and moved to the RHR. The receiver section is controlled by the Line Control Register ...
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... NXP Semiconductors [1] FIFO reset requires at least two XTAL1 clocks, therefore, they cannot be reset without the presence of the XTAL1 clock. 8.4 Line Control Register (LCR) This register controls the data communication format. The word length, number of stop bits, and parity type are selected by writing the appropriate bits to the LCR. ...
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... NXP Semiconductors Table 13. LCR[ Table 14. LCR[ Table 15. LCR[ SC16IS740_750_760_5 Product data sheet Single UART with I LCR[5] parity selection LCR[4] LCR[3] Parity selection parity 0 1 odd parity 1 1 even parity 0 1 forced parity ‘1’ forced parity ‘0’ ...
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... NXP Semiconductors 8.5 Line Status Register (LSR) Table 16 Table 16. Bit When the LSR is read, LSR[4:2] reflect the error bits (BI, FE, PE) of the character at the top of the RX FIFO (next character to be read). Therefore, errors in a character are identified by reading the LSR and then reading the RHR. ...
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... NXP Semiconductors 8.6 Modem Control Register (MCR) The MCR controls the interface with the mode, data set, or peripheral device that is emulating the modem. Table 17. Bit [1] MCR[7:5] and MCR[2] can only be modified when EFR[4] is set, that is, EFR[ write enable. ...
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... NXP Semiconductors 8.7 Modem Status Register (MSR) This 8-bit register provides information about the current state of the control lines from the modem, data set, or peripheral device to the host. It also indicates when a control input from the modem changes state. Table 18. Bit ...
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... NXP Semiconductors 8.8 Interrupt Enable Register (IER) The Interrupt Enable Register (IER) enables each of the six types of interrupt, receiver error, RHR interrupt, THR interrupt, modem status, Xoff received, or CTS/RTS change of state from LOW to HIGH. The IRQ output signal is activated in response to interrupt generation. ...
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... NXP Semiconductors 8.9 Interrupt Identification Register (IIR) The IIR is a read-only 8-bit register which provides the source of the interrupt in a prioritized manner. Table 20. Bit 7:6 5:1 0 Table 21. Priority level [1] Modem interrupt status must be read via MSR register and GPIO interrupt status must be read via IOState register ...
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... NXP Semiconductors 8.10 Enhanced Features Register (EFR) This 8-bit register enables or disables the enhanced features of the UART. the enhanced feature register bit settings. Table 22. Bit 3:0 8.11 Division registers (DLL, DLH) These are two 8-bit registers which store the 16-bit divisor for generation of the baud clock in the baud rate generator. DLH stores the most signifi ...
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... NXP Semiconductors 8.12 Transmission Control Register (TCR) This 8-bit register is used to store the RX FIFO threshold levels to stop/start transmission during hardware/software flow control. settings. Table 23. Bit 7:4 3:0 TCR trigger levels are available from characters with a granularity of four. Remark: TCR can only be written to when EFR[ and MCR[ The programmer must program the TCR such that TCR[3:0] > ...
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... NXP Semiconductors 8.15 Receiver FIFO Level register (RXLVL) This register is a read-only register, it reports the fill level of the receive FIFO. That is, the number of characters in the RX FIFO. Table 26. Bit 7 6:0 8.16 Programmable I/O pins Direction register (IODir) This register is only available on the SC16IS750 and SC16IS760. This register is used to program the I/O pins direction ...
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... NXP Semiconductors 8.19 I/O Control register (IOControl) This register is only available on the SC16IS750 and SC16IS760. Table 30. Bit 7 Remark: As I/O pins, the direction, state, and interrupt of GPIO4 to GPIO7 are controlled by the following registers: IODir, IOState, IOIntEna, and IOControl. The state of CD, RI, DSR pins will not be reflected in MSR[7:5] or MSR[3:1], and any change of state on these three pins will not trigger a modem status interrupt (even if enabled via IER[3]), and the state of the DTR pin cannot be controlled by MCR[0] ...
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... NXP Semiconductors 8.20 Extra Features Control Register (EFCR) Table 31. Bit [1] For SC16IS760 only. 9. RS-485 features 9.1 Auto RS-485 RTS control Normally the RTS pin is controlled by MCR bit hardware flow control is enabled, the logic state of the RTS pin is controlled by the hardware flow control circuitry. EFCR register bit 4 will take the precedence over the other two modes ...
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... NXP Semiconductors 9.2 RS-485 RTS output inversion EFCR bit 5 reverses the polarity of the RTS pin if the UART is in auto RS-485 RTS mode. When the transmitter has data to be sent it will deasserts the RTS pin (logic 1), and when the last bit of the data has been sent out the transmitter asserts the RTS pin (logic 0). ...
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... NXP Semiconductors 2 10. I C-bus operation The two lines of the I lines are connected to a positive supply via a pull-up resistor, and remain HIGH when the bus is not busy. Each device is recognized by a unique address whether microcomputer, LCD driver, memory or keyboard interface and can operate as either a transmitter or receiver, depending on the function of the device ...
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... NXP Semiconductors SDA MSB SCL START condition 2 Fig 18. Data transfer on the I C-bus data output by transmitter data output by receiver SCL from master S START condition 2 Fig 19. Acknowledge on the I C-bus A slave receiver must generate an acknowledge after the reception of each byte, and a master must generate one after the reception of each byte clocked out of the slave transmitter. There are two exceptions to the ‘ ...
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... NXP Semiconductors An address on the network is seven bits long, appearing as the most significant bits of the address byte. The last bit is a direction (R/W) bit. A ‘0’ indicates that the master is transmitting (write) and a ‘1’ indicates that the master requests data (read). A complete data transfer, comprised of an address byte indicating a ‘ ...
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... NXP Semiconductors master write: S SLAVE ADDRESS START condition master read: S SLAVE ADDRESS START condition combined S SLAVE ADDRESS formats: START condition read or 2 Fig 21. I C-bus data formats SC16IS740_750_760_5 Product data sheet Single UART with I data transferred (n bytes + acknowledge DATA A write ...
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... NXP Semiconductors 10.3 Addressing Before any data is transmitted or received, the master must send the address of the receiver via the SDA line. The first byte after the START condition carries the address of the slave device and the read/write bit. address can be selected by using A1 and A0 pins. For example, if these 2 pins are connected to V communicates with it through this address ...
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... NXP Semiconductors Table 33 SPI interfaces. Bit 0 is not used, bits 2:1 select the channel, bits 6:3 select one of the UART internal registers. Bit 7 is not used with the I SPI interface to indicate a read or a write operation. S SLAVE ADDRESS White block: host to SC16IS740/750/760 Grey block: SC16IS740/750/760 to host ...
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SCLK CH1 CH0 X R/W R A[3:0] = register address; CH1 = 0, CH0 = 0 a. Register write SCLK CH1 CH0 X SI R ...
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... NXP Semiconductors Table 34. Bit 7 6:3 2:1 0 12. Limiting values Table 35. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol tot P/out T amb stg [1] 5.5 V steady state voltage tolerance on inputs and outputs is valid only when the supply voltage is present. ...
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... NXP Semiconductors 13. Static characteristics Table 36. Static characteristics V = 2 amb Symbol Parameter Supplies V supply voltage DD I supply current DD Inputs I2C/SPI, RX, CTS V HIGH-level input voltage IH V LOW-level input voltage IL I leakage current L C input capacitance i Outputs TX, RTS HIGH-level output voltage ...
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... NXP Semiconductors Table 36. Static characteristics V = 2 amb Symbol Parameter 2 I C-bus inputs SCL, CS/A0, SI/A1 V HIGH-level input voltage IH V LOW-level input voltage IL I leakage current L C input capacitance i [2] Clock input XTAL1 V HIGH-level input voltage IH V LOW-level input voltage ...
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... NXP Semiconductors 14. Dynamic characteristics 2 Table 37. I C-bus timing specifications All the timing limits are valid within the operating supply voltage, ambient temperature range and output load 2 amb an input voltage All output load = 25 pF, except SDA output load = 400 pF. ...
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... NXP Semiconductors RESET Fig 25. SCL delay after reset START protocol condition (S) t SU;STA SCL t BUF SDA t HD;STA Rise and fall times refer Fig 26. I C-bus timing diagram SDA GPIOn Fig 27. Write to output (SC16IS750 and SC16IS760 only) SLAVE ADDRESS SDA IRQ MODEM pin Fig 28 ...
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... NXP Semiconductors SLAVE ADDRESS SDA IRQ GPIOn Fig 29. GPIO pin interrupt (SC16IS750 and SC16IS760 only) RX IRQ Fig 30. Receive interrupt SLAVE ADDRESS SDA IRQ Fig 31. Receive interrupt clear SLAVE ADDRESS SDA IRQ Fig 32. Transmit interrupt clear SC16IS740_750_760_5 Product data sheet Single UART with I ...
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... NXP Semiconductors Table 38. f dynamic characteristics XTAL V = 2 amb Symbol Parameter t clock pulse duration w1 t clock pulse duration w2 f frequency on pin XTAL XTAL [1] Applies to external clock, crystal oscillator max. 24 MHz ------- [2] XTAL t w3 EXTERNAL CLOCK Fig 33. External clock timing Table 39. SC16IS740/750 SPI-bus timing specifi ...
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... NXP Semiconductors Table 40. SC16IS760 SPI-bus timing specifications All the timing limits are valid within the operating supply voltage, ambient temperature range and output load 2 amb an input voltage All output load = 25 pF, unless otherwise specified. ...
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... NXP Semiconductors CS SCLK R/W GPIOx R A[3:0] = IOState (0x0B); CH1 = 0; CH0 = 0 Fig 35. SPI write IOState to GPIO switch (SC16IS750 and SC16IS760 only) CS SCLK SI A3 R/W DTR (GPIO5) R A[3:0] = MCR (0x04); CH1 = 0; CH0 = 0 Fig 36. SPI write MCR to DTR output switch (SC16IS750 and SC16IS760 only) CS SCLK R/W SO IRQ R ...
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... NXP Semiconductors CS SCLK R/W SO IRQ R A[3:0] = MSR (0x06); CH1 = 0; CH0 = 0 Fig 38. Read MSR to clear modem INT (SC16IS750 and SC16IS760 only) CS SCLK R/W SO IRQ R A[3:0] = IOState (0x0B); CH1 = 0; CH0 = 0 Fig 39. Read IOState to clear GPIO INT (SC16IS750 and SC16IS760 only) CS SCLK R/W SO IRQ R ...
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... NXP Semiconductors 15. Package outline TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 0.85 mm terminal 1 index area terminal 1 24 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 16. Handling information Inputs and outputs are protected against electrostatic discharge in normal handling. However completely safe you must take normal precautions appropriate to handling integrated circuits. 17. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” ...
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... NXP Semiconductors • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 17.4 Reflow soldering Key characteristics in reflow soldering are: • ...
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... NXP Semiconductors Fig 44. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 18. Abbreviations Table 43. Acronym CPU FIFO GPIO 2 I C-bus IrDA LCD MIR POR SIR SPI ...
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... NXP Semiconductors 19. Revision history Table 44. Revision history Document ID Release date SC16IS740_750_760_5 20061116 • Modifications: Section 2 to “ +95 C“ • Section 10.4 “Use of • Figure 22 “Master writes to • Figure 23 “Master read from • Table 16 “Line Status Register bits “0x00” ...
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... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...
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... NXP Semiconductors 22. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 General features . . . . . . . . . . . . . . . . . . . . . . . . 1 2 2.2 I C-bus features . . . . . . . . . . . . . . . . . . . . . . . . 2 2.3 SPI features . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 Functional description . . . . . . . . . . . . . . . . . . . 9 7.1 Trigger levels 7.2 Hardware flow control . . . . . . . . . . . . . . . . . . . . 9 7.2.1 Auto RTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.2.2 Auto CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.3 Software flow control . . . . . . . . . . . . . . . . . . . 11 7 ...