sc16is850l NXP Semiconductors, sc16is850l Datasheet
sc16is850l
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sc16is850l Summary of contents
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... I bidirectional. The SC16IS850L supports SPI clock speeds Mbit/s, and it supports IrDA SIR up to 115.2 kbit/s. Its internal register set is backward-compatible with the widely used and widely popular 16C850. This allows the software to be easily written or ported from another platform ...
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... All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2011 SC16IS850L 2 Single UART with I C-bus/SPI interface © NXP B.V. 2011. All rights reserved. ...
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... Block diagram of SC16IS850L I SC16IS850L RESET SCLK CS SO SPI SI IRQ 1 kΩ (1 I2C/SPI XTAL1 Block diagram of SC16IS850L SPI interface All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2011 SC16IS850L 2 Single UART with I C-bus/SPI interface V DD 16C450 COMPATIBLE REGISTER SETS MODEM ...
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... UART clear to send (active LOW). A logic 0 (LOW) on the CTS pin indicates the modem or data set is ready to accept transmit data from the SC16IS850L. Status can be tested by reading MSR[4]. This pin only affect the transmit and receive operations when Auto-CTS function is enabled via the Enhanced Feature Register EFR[7] for hardware flow control operation ...
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... I All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2011 SC16IS850L 2 Single UART with I C-bus/SPI interface Description Power ground C-bus or SPI interface select C-bus interface is selected if this pin is at logic HIGH. SPI interface is selected if this pin is at logic LOW ...
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... 12, 23 All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2011 SC16IS850L 2 Single UART with I C-bus/SPI interface Description UART request to send (active LOW). A logic 0 on the RTS pin indicates the transmitter has data ready and waiting to send. Writing a ...
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... SC16IS850L is fabricated with an advanced CMOS process. The SC16IS850L provides a single UART capability with 128 bytes of transmit and receive FIFO memory, instead of 64 bytes for the SC16IS750. The SC16IS850L is designed to work with high speed modems and shared network environments that require fast data processing time. ...
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... NXP Semiconductors 7.2 Internal registers The SC16IS850L provides a set of 25 internal registers for monitoring and controlling the functions of the UART. These registers are shown in Table General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LCR/LSR, EFCR, SPR ...
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... Automatic hardware flow control is selected by setting EFR[6] (RTS) and EFR[7] (CTS logic 1. If CTS transitions from a logic logic 1 indicating a flow control request, ISR[5] will be set to a logic 1 (if enabled via IER[7:6]), and the SC16IS850L will suspend TX transmissions as soon as the stop bit of the character in process is shifted out. ...
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... When a match occurs, ISR bit 4 will be set (if enabled via IER[5]) and the interrupt output pin (if receive interrupt is enabled) will be activated. Following a suspension due to a match of the Xoff characters’ values, the SC16IS850L will monitor the receive data stream for a match to the Xon1/Xon2 character value(s match is found, the SC16IS850L will resume operation and clear the flags (ISR[4]) ...
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... Interrupt priority and time-out interrupts The interrupts are enabled by IER[7:0]. Care must be taken when handling these interrupts. Following a reset, if Interrupt Enable Register (IER) bit the SC16IS850L will issue a Transmit Holding Register interrupt. This interrupt must be serviced prior to continuing operations. The ISR indicates the current singular highest priority interrupt only ...
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... The generator divides the input 16 clock by any divisor from SC16IS850L divides the basic external clock by 16. The baud rate is configured via the CLKPRES, DLL and DLM internal register functions. Customized baud rates can be achieved by selecting the proper divisor values for the MSB and LSB sections of the baud rate generator ...
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... All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2011 SC16IS850L 2 Single UART with I C-bus/SPI interface XTAL2 XTAL1 1.5 kΩ X1 1.8432 MHz 24 MHz XTAL1 XTAL2 002aac630 DLM ...
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... Product data sheet 8). MCR[3:0] register bits are used for controlling loopback diagnostic testing. Section 8.2.2) to send and receive data. All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2011 SC16IS850L 2 Single UART with I C-bus/SPI interface © NXP B.V. 2011. All rights reserved ...
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... CONTROL LOGIC RECEIVE FIFO REGISTERS FLOW CONTROL LOGIC CLOCK AND BAUD RATE GENERATOR XTAL1 XTAL2 All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2011 SC16IS850L 2 Single UART with I C-bus/SPI interface TRANSMIT TX SHIFT REGISTER IR ENCODER RECEIVE SHIFT RX REGISTER IR DECODER ...
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... Refer to application note AN19064, “How to wake up SC16IS740/750/760 in IrDA mode” for a software procedure to wake up the device by receiving data in IrDA mode. When the SC16IS850L is in Sleep mode and the host data bus (D[7:0], A[2:0], IOW, IOR, CS) remains in steady state, either HIGH or LOW, the Sleep mode supply current will be in the ...
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... ID address, the controller takes no further action, and the receiver will receive the subsequent data. SC16IS850L Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2011 SC16IS850L 2 Single UART with I C-bus/SPI interface © NXP B.V. 2011. All rights reserved ...
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... Register descriptions Table 6 assigned bit functions are more fully defined in SC16IS850L Product data sheet details the assigned bit functions for the SC16IS850L internal registers. The All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2011 SC16IS850L 2 Single UART with I C-bus/SPI interface Section 8 ...
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... Table 6. SC16IS850L internal registers [ Register Default Bit 7 [2] General register set RHR 0xXX bit THR 0xXX bit IER 0x00 CTS [3] interrupt FCR 0x00 RCVR trigger (MSB ISR 0x01 FIFOs enabled LCR ...
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... Table 6. SC16IS850L internal registers …continued [ Register Default Bit 7 [5] Enhanced feature register set EFR 0x00 Auto CTS Xon1 0x00 bit Xon2 0x00 bit Xoff1 0x00 bit Xoff2 0x00 bit 15 [7] First extra feature register set ...
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... CTS pin transitions from a logic logic 1. RTS interrupt. logic 0 = disable the RTS interrupt (normal default condition) logic 1 = enable the RTS interrupt. The SC16IS850L issues an interrupt when the RTS pin transitions from a logic logic 1. Xoff interrupt. logic 0 = disable the software flow control, receive Xoff interrupt (normal default ...
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... ISR loading the THR with new data characters. 8.2.2 IER versus Receive/Transmit FIFO polled mode operation When FCR[0] = logic 1, setting IER[3:0] puts the SC16IS850L in the FIFO polled mode of operation. In this mode, interrupts are not generated and the user must poll the LSR register for TX and/or RX data status ...
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... FCR[5:4] Transmit trigger level in 32-byte FIFO mode These bits are used to set the trigger level for the transmit FIFO interrupt and flow control. The SC16IS850L will issue a transmit empty interrupt when the number of characters in FIFO drops below the selected trigger level. Refer to Table 10 ...
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... RXINTLVL, TXINTLVL registers (see 8.4 Interrupt Status Register (ISR) The SC16IS850L provides six levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced ...
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... Stop bit length (bit times ⁄ All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2011 SC16IS850L 2 Single UART with I C-bus/SPI interface …continued Table 14). Table 15). Table 16). © NXP B.V. 2011. All rights reserved ...
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... MCR[4] Loopback. Enable the local loopback mode (diagnostics). In this mode the transmitter output (TX) and the receiver input (RX), CTS, DSR, CD, and RI are disconnected from the SC16IS850L I/O pins. Internally the modem data and control pins are connected into a loopback data configuration (see Figure 8) ...
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... NXP Semiconductors 8.7 Line Status Register (LSR) This register provides the status of data transfers between the SC16IS850L and the CPU. Table 18. Bit Symbol 7 LSR[7] 6 LSR[6] 5 LSR[5] 4 LSR[4] 3 LSR[3] 2 LSR[2] 1 LSR[1] 0 LSR[0] SC16IS850L Product data sheet Line Status Register bits description Description FIFO data error. ...
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... A modem Status Interrupt will be generated. RI [1] MSR[2] logic change (normal default condition) logic 1 = the RI input to the SC16IS850L has changed from a logic logic 1. A modem Status Interrupt will be generated. DSR [1] MSR[1] logic DSR change (normal default condition) logic 1 = the DSR input to the SC16IS850L has changed state since the last time it was read ...
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... Remark: EFCR[2:1] has higher priority than EFCR[0]. TXLVLCNT and RXLVLCNT can only be accessed if EFCR[2:1] are zeroes. 8.10 Scratchpad Register (SPR) The SC16IS850L provides a temporary data register to store 8 bits of user information. 8.11 Divisor Latch (DLL and DLM) These are two 8-bit registers which store the 16-bit divisor for generation of the baud clock in the baud rate generator ...
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... Special Character Detect. logic 0 = special character detect disabled (normal default condition) logic 1 = special character detect enabled. The SC16IS850L compares each incoming receive character with Xoff2 data match exists, the received data will be transferred to FIFO and ISR[4] will be set to indicate detection of special character ...
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... This register stores the programmable receive interrupt trigger levels for 128-byte FIFO mode 0x00 = trigger level is set to 1 0x01 = trigger level is set to 1 ... 0x80 = trigger level is set to 128 All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2011 SC16IS850L 2 Single UART with I C-bus/SPI interface [1] [1] . [1] . © ...
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... Symbol Description CLKPRES[7:4] reserved CLKPRES[3:0] Clock Prescaler value. Reset to 0. All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2011 SC16IS850L 2 Single UART with I C-bus/SPI interface Table 25 shows the FLWCNTH Table 26 shows the FLWCNTL © NXP B.V. 2011. All rights reserved. ...
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... AFCR2[0] 9-bitMode. Enable 9-bit mode or Multidrop (RS-485) mode logic 0 = normal RS-232 mode logic 1 = enable 9-bit mode All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2011 SC16IS850L 2 Single UART with I C-bus/SPI interface © NXP B.V. 2011. All rights reserved ...
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... FIFO falls below the trigger level, or becomes empty and the last stop bit has been shifted out of the Transmit Shift Register. All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2011 SC16IS850L 2 Single UART with I C-bus/SPI interface [1] © ...
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... NXP Semiconductors 8.23 SC16IS850L external reset condition and software reset These two reset methods are identical and will reset the internal registers as indicated in Table 31. Table 31. Register IER FCR ISR LCR MCR LSR MSR EFCR SPR DLL DLM TXLVLCNT RXLVLCNT EFR Xon1 Xon2 ...
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... Bit transfer on the I C-bus SDA SCL S START condition 11). The clock pulse related to the acknowledge bit is generated by the All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2011 SC16IS850L 2 Single UART with I C-bus/SPI interface Figure 9). The data on the SDA change of data allowed ...
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... C-bus C-bus All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2011 SC16IS850L 2 Single UART with I C-bus/SPI interface ACK clock line held LOW while interrupt is serviced transmitter stays off of the bus ...
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... C-bus network has a unique seven-bit address. The address of a 13, where the R/W bit could indicate either direction. After completing the Figure 14. Note that the repeated START allows for both change of a All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2011 SC16IS850L 2 Single UART with I C-bus/SPI interface ...
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... SDA line. The first byte after the START condition carries the address of the slave device and the read/write bit. can be selected by using A1 and A0 pins. For example, if these 2 pins are connected then the SC16IS850L’s address is set to 0x90, and the master communicates with it DD through this address. Table 33. ...
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... The last byte of the read cycle will be followed by a negative acknowledge, signalling the end of transfer. The cycle is terminated by a STOP signal. S SLAVE ADDRESS White block: host to SC16IS850L Grey block: SC16IS850L to host (1) See Table 34 for additional information. Fig 16. Master read from slave SC16IS850L Product data sheet shows the breakdown of the subaddress (register address) byte ...
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... Register address byte (I C) Name Function - not used A[2:0] UART’s internal register select - not used; set to 0 All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2011 SC16IS850L 2 Single UART with I C-bus/SPI interface © NXP B.V. 2011. All rights reserved ...
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SCLK CH0 X SI R/W A0 CH1 R A[2:0] = register address; CH1 = 0, CH0 = don’t care a. Register write SCLK CH1 ...
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... V. Conditions operating; no load MHz = 800 1 All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2011 SC16IS850L 2 Single UART with I C-bus/SPI interface Min Max - 2.5 0 40 +85 ...
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... XTAL2 should be left open when XTAL1 is driven by an external clock. SC16IS850L Product data sheet …continued Conditions inputs are ground DD All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2011 SC16IS850L 2 Single UART with I C-bus/SPI interface Min Typ Max 0.7 0.3 ...
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... Product data sheet [1] and V with an input voltage Conditions SCL LOW to data out valid All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2011 SC16IS850L 2 Single UART with I C-bus/SPI interface All output load SS DD Standard mode Fast mode 2 ...
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... SU;DAT HD;STA HD;DAT and MSR REGISTER t d2 All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2011 SC16IS850L Single UART with I d15 002aab437 bit 0 STOP acknowledge LSB condition (A) (R/W) ( VD;DAT VD;ACK SU;STO ...
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... RHR SLAVE ADDRESS THR REGISTER All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2011 SC16IS850L 2 Single UART with I C-bus/SPI interface next stop start bit bit 002aab258 R A DATA t d7 ...
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... XTAL1 t w clk Fig 24. External clock timing Table 40. SC16IS850L SPI-bus timing specifications All the timing limits are valid within the operating supply voltage, ambient temperature range and output load; + 1. 1.95 V, and refer to V ...
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... Product data sheet CH1 CH0 CH1 CH0 All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2011 SC16IS850L 2 Single UART with I C-bus/SPI interface t CSH d10 ...
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... CH0 d12 A1 A0 CH1 CH0 d14 All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2011 SC16IS850L 2 Single UART with I C-bus/SPI interface © NXP B.V. 2011. All rights reserved. 002aab441 ...
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... Product data sheet start TX data bit time bit time start All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2011 SC16IS850L 2 Single UART with I UART frame data bits bit time 16× clock delay 1 ...
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... 4.1 2.75 4.1 2.75 0.5 2.5 3.9 2.45 3.9 2.45 REFERENCES JEDEC JEITA MO-220 - - - All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2011 SC16IS850L 2 Single UART with I C-bus/SPI interface detail 0.5 0.05 0.1 2.5 0.1 0.05 0.3 EUROPEAN ...
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... 2.5 scale (1) ( 0.30 0.2 7.9 4.5 0.65 0.19 0.1 7.7 4.3 REFERENCES JEDEC JEITA MO-153 All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2011 SC16IS850L 2 Single UART with detail 6.6 0.75 0.4 1 ...
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... Solder bath specifications, including temperature and impurities SC16IS850L Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2011 SC16IS850L 2 Single UART with I C-bus/SPI interface © NXP B.V. 2011. All rights reserved ...
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... Package reflow temperature (C) 3 Volume (mm ) < 350 260 260 250 Figure 34. All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2011 SC16IS850L 2 Single UART with I C-bus/SPI interface Figure 34) than a SnPb process, thus 350 220 220 350 to 2000 > 2000 260 ...
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... Least Significant Bit Most Significant Bit Serial InfraRed Serial Peripheral Interface Universal Asynchronous Receiver/Transmitter All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2011 SC16IS850L 2 Single UART with I C-bus/SPI interface peak temperature 001aac844 © NXP B.V. 2011. All rights reserved. ...
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... NXP Semiconductors 17. Revision history Table 44. Revision history Document ID Release date SC16IS850L v.1 20110722 SC16IS850L Product data sheet Data sheet status Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2011 SC16IS850L 2 Single UART with I C-bus/SPI interface Change notice ...
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... Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2011 SC16IS850L 2 Single UART with I C-bus/SPI interface © NXP B.V. 2011. All rights reserved. ...
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... I C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 1 — 22 July 2011 SC16IS850L 2 Single UART with I C-bus/SPI interface © NXP B.V. 2011. All rights reserved ...
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... Flow Control Trigger Level Low (FLWCNTL 8.19 Clock Prescaler (CLKPRES 8.20 RS-485 Turn-around time delay (RS485TIME) 33 8.21 Advanced Feature Control Register 2 (AFCR2 8.22 Advanced Feature Control Register 1 (AFCR1 8.23 SC16IS850L external reset condition and software reset . . . . . . . . . . . . . . . . . . . . . . . . C-bus operation . . . . . . . . . . . . . . . . . . . . . . 36 9.1 Data transfers . . . . . . . . . . . . . . . . . . . . . . . . 36 9.2 Addressing and transfer formats . . . . . . . . . . 37 9.3 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9 ...