sc16is850l NXP Semiconductors, sc16is850l Datasheet - Page 40

• Manufacturer Part Number: sc16is850l
• Description: Single Uart With I2c-bus/spi Interface, 128 Bytes Of Transmit And Receive Fifos, Irda Sir Built-in Support
• Manufacturer: NXP Semiconductors

NXP Semiconductors
SC16IS850L
Product data sheet
Fig 15. Master writes to slave
Fig 16. Master read from slave
(1) See
(1) See
S
White block: host to SC16IS850L
Grey block: SC16IS850L to host
White block: host to SC16IS850L
Grey block: SC16IS850L to host
SLAVE ADDRESS
Table 34
Table 34
S
for additional information.
for additional information.
SLAVE ADDRESS
locations for a multi-byte transfer. A subaddress is an 8-bit byte. Unlike the device
address, it does not contain a direction (R/W) bit, and like any byte transferred on the bus
it must be followed by an acknowledge.
Table 34
not used, bits [5:3] are used to select one of the device’s internal registers, and bits [7:6]
are not used.
A register write cycle is shown in
byte with the direction bit set to ‘write’, a subaddress byte, a number of data bytes, and a
STOP signal. The subaddress indicates which register the master wants to access, and
the data bytes which follow will be written one after the other to the subaddress location.
Table 34
SPI interfaces. Bit 0 is not used, bits 2:1 select the channel, bits 6:3 select one of the
UART internal registers. Bit 7 is not used with the I
SPI interface to indicate a read or a write operation.
The register read cycle (see
sending a slave address with the direction bit set to ‘write’ with a following subaddress.
Then, in order to reverse the direction of the transfer, the master issues a repeated
START followed again by the device address, but this time with the direction bit set to
‘read’. The data bytes starting at the internal subaddress will be clocked out of the device,
each followed by a master-generated acknowledge. The last byte of the read cycle will be
followed by a negative acknowledge, signalling the end of transfer. The cycle is
terminated by a STOP signal.
W
shows the breakdown of the subaddress (register address) byte. Bits [2:0] are
and
Table 35
A
All information provided in this document is subject to legal disclaimers.
W
REGISTER ADDRESS
show the bits’ presentation at the subaddress byte for I
A
Rev. 1 — 22 July 2011
REGISTER ADDRESS
Figure
Figure
(1)
16) commences in a similar manner, with the master
A
15. The START is followed by a slave address
nDATA
(1)
S
Single UART with I
A
2
SLAVE ADDRESS
C-bus interface, but it is used by the
A
nDATA
LAST DATA
SC16IS850L
A
2
002aab047
C-bus/SPI interface
R
© NXP B.V. 2011. All rights reserved.
P
NA
A
2
002aab048
C-bus and
P
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