adum3220 Analog Devices, Inc., adum3220 Datasheet - Page 4

• Manufacturer Part Number: adum3220
• Description: 4 A Dual-channel Gate Driver Adum3220
• Manufacturer: Analog Devices, Inc.

ADuM3220
ELECTRICAL CHARACTERISTICS—3.3 V OPERATION
All voltages are relative to their respective ground. 3.0 V ≤ V
maximum specifications apply over T
specifications are tested with CMOS signal levels.
Table 2.
Parameter
DC SPECIFICATIONS
SWITCHING SPECIFICATIONS
1
2
3
4
5
6
7
Short-circuit duration less than 1 μs. Average power must conform to the limit shown under the
The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the
Figure 8 and Figure 9 for total V
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
T
measured from the 10% level of the falling edge of the V
delay parameters.
t
load within the recommended operating conditions. See Figure 17 for waveforms of propagation delay parameters.
Channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.
PSK
DLH
Input Supply Current, Two Channels, Quiescent
Output Supply Current, Two Channels, Quiescent
Total Supply Current, Two Channels
Input Currents
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Logic Low Output Voltages
Undervoltage Lockout, V
Output Short-Circuit Pulsed Current
Pulse Width
Data Rate
Propagation Delay
Propagation Delay Skew
Channel-to-Channel Matching
Output Rise/Fall Time (10% to 90%)
Dynamic Input Supply Current per Channel
Dynamic Output Supply Current per Channel
Refresh Rate
is the magnitude of the worst-case difference in t
propagation delay is measured from the 90% level of the rising edge of the V
Positive Going Threshold
Negative Going Threshold
Hysteresis
DC to 1 MHz
V
V
DD1
DD2
Supply Current
Supply Current
4
3
5
6
DD2
Supply
DD1
7
and V
1
2
DD2
supply currents as a function of data rate.
J
= −40°C to 125°C. All typical specifications are at T
DLH
and/or t
Ix
signal to the 90% level of the falling edge of the V
Symbol
I
I
I
I
I
V
V
V
V
V
V
V
I
PW
t
t
t
t
t
t
t
I
I
f
DDI(Q)
DDO(Q)
DD1(Q)
DD2(Q)
IA
OA(SC)
DDI(D)
DDO(D)
DLH,
DLH,
PSK
PSKCD
PSKCD
R
R
r
IH
IL
OAH
OAL
DD2UV+
DD2UV−
DD2UVH
/t
/t
, I
F
F
IB
, V
, V
t
t
DHL
, I
DHL
DHL
OBL
OAH
OB(SC)
that is measured between units at the same operating temperature, supply voltages, and output
DD1
Rev. 0 | Page 4 of 16
Min
−10
0.7 × V
V
3.7
3.2
2.0
100
36
37
14
14
DD2
≤ 3.6 V, 4.5 V ≤ V
− 0.1
DD1
Ix
signal to the 10% level of the rising edge of the V
Typ
0.7
4.7
0.8
11
+0.01
V
0.0
4.1
3.7
0.4
4.0
48
53
1
1
20
22
0.025
1.5
1.1
DD2
.Absolute Maximum Ratings
DD2
Max
1.0
10
1.0
17
+10
0.3 × V
0.15
4.4
4.1
1
62
72
12
5
7
25
28
≤ 18 V, unless stated otherwise. All minimum/
DD1
Ox
J
= 25°C, V
signal. See Figure 17 for waveforms of propagation
Unit
mA
mA
mA
mA
μA
V
V
V
V
V
V
V
A
ns
MHz
ns
ns
ns
ns
ns
ns
ns
mA/Mbps
mA/Mbps
Mbps
DD1
.
= 3.3 V, V
Power Consumption
Test Conditions
DC to 1 MHz logic signal
frequency
DC to 1 MHz logic signal frequency
0 ≤ V
I
I
V
C
C
C
C
C
C
C
C
C
V
V
Ox
Ox
DD2
L
L
L
L
L
L
L
L
L
DD2
DD2
Ox
= 2 nF, V
= 2 nF, V
= 2 nF, V
= 2 nF, V
= 2 nF, V
= 2 nF, V
= 2 nF, V
= 2 nF, V
= 2 nF, V
= −20 mA, V
= +20 mA, V
signal. t
= 10 V
= 10 V
= 10 V
IA
, V
DD2
IB
DD2
DD2
DD2
DD2
DD2
DD2
DD2
DD2
DD2
≤ V
DHL
= 10 V. Switching
= 10 V
= 10 V
= 10 V; see Figure 17
= 4.5 V; see Figure 17
= 10 V; see Figure 17
= 10 V; see Figure 17
= 4.5 V; see Figure 17
= 10 V; see Figure 17
= 4.5 V; see Figure 17
DD1
propagation delay is
Ix
Ix
= V
= V
section. See
IxH
IxL