cyrf6936 Cypress Semiconductor Corporation., cyrf6936 Datasheet - Page 4

• Manufacturer Part Number: cyrf6936
• Description: Wirelessusb Lp 2.4 Ghz Radio Soc
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-16015 Rev. *G
Packet Buffers
All data transmission and reception uses the 16 byte packet
buffers—one for transmission and one for reception.
The transmit buffer allows a complete packet of up to 16 bytes
of payload data to be loaded in one burst SPI transaction, and
then transmitted with no further MCU intervention. Similarly,
the receive buffer allows an entire packet of payload data up
to 16 bytes to be received with no firmware intervention
required until packet reception is complete.
The CYRF6936 IC supports packets up to 255 bytes.
However, actual maximum packet length depends on the
accuracy of the clock on each end of the link and the data
mode; interrupts are provided to allow an MCU to use the
transmit and receive buffers as FIFOs. When transmitting a
packet longer than 16 bytes, the MCU can load 16 bytes
initially, and add further bytes to the transmit buffer as trans-
mission of data creates space in the buffer. Similarly, when
receiving packets longer than 16 bytes, the MCU must fetch
received data from the FIFO periodically during packet
reception to prevent it from overflowing.
Auto Transaction Sequencer (ATS)
The CYRF6936 IC provides automated support for trans-
mission and reception of acknowledged data packets.
When transmitting in transaction mode, the device automati-
cally:
Similarly, when receiving in transaction mode, the device
automatically:
The contents of the packet buffers are not affected by the
transmission or reception of ACK packets.
In each case, the entire packet transaction takes place without
any need for MCU firmware action (as long as packets of 16
bytes or less are used); to transmit data the MCU simply must
load the data packet to be transmitted, set the length, and set
the TX GO bit. Similarly, when receiving packets in transaction
mode, firmware simply must retrieve the fully received packet
• Starts the crystal and synthesizer
• Enters transmit mode
• Transmits the packet in the transmit buffer
• Transitions to receive mode and waits for an ACK packet
• Transitions to the transaction end state when either an ACK
• Waits in receive mode for a valid packet to be received
• Transitions to transmit mode, transmits an ACK packet
• Transitions to the transaction end state (receive mode to
packet is received, or a timeout period expires
await the next packet, and so on.)
P r e a m b l e
n x 1 6 u s
P
1 s t F r a m i n g
S O P 1
S y m b o l *
2 n d F r a m i n g
S y m b o l *
S O P 2
Figure 3. Example ACK Packet Format
r e c e i v e d p a c k e t .
C R C f i e l d f r o m
2 B y t e p e r i o d s
C R C 1 6
in response to an interrupt request indicating reception of a
packet.
Backward Compatibility
The CYRF6936 IC is fully interoperable with the main modes
of the first generation devices. The 62.5 kbps mode is
supported by selecting 32 chip DDR mode. Similarly, the
15.675 kbps mode is supported by selecting 64 chip SDR
mode.
In this way, a suitably configured CYRF6936 IC device may
transmit data to or receive data from a first generation device,
or both. Backwards compatibility requires disabling the SOP,
length, and CRC16 fields.
Data Rates
By combining the PN code lengths and data transmission
modes described previously, the CYRF6936 IC supports the
following data rates:
Functional Block Overview
2.4 GHz Radio
The radio transceiver is a dual conversion low IF architecture
optimized for power and range/robustness. The radio employs
channel-matched filters to achieve high performance in the
presence of interference. An integrated Power Amplifier (PA)
provides up to +4 dBm transmit power, with an output power
control range of 34 dB in seven steps. The supply current of
the device is reduced as the RF output power is reduced.
Table 1. Internal PA Output Power Step Table
• 1000 kbps (GFSK)
• 250 kbps (32 chip 8DR)
• 125 kbps (64 chip 8DR)
• 62.5 kbps (32 chip DDR)
• 31.25 kbps (64 chip DDR)
• 15.625 kbps (64 chip SDR)
PA Setting
7
6
5
4
3
2
1
0
* N o t e : 3 2 o r 6 4 u s
Typical Output Power (dBm)
CYRF6936
–13
–18
–24
–30
–35
+4
–5
0
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