ak4527b AKM Semiconductor, Inc., ak4527b Datasheet
ak4527b
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ak4527b Summary of contents
Page 1
... ADC for passing audio data to the primary audio output port. Control may be set directly by pins or programmed through a separate serial interface. The AK4527B has a dynamic range of 102dB for ADC, 106dB for DAC and is well suited for digital surround for home theater and car audio. An AC-3 system can be built with a IEC60958(SPDIF) receiver such as the AK4112A ...
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... MS0056-E-00 Audio I/F HPF HPF DATT MCLK LRCK BICK DATT DATT Format Converter DATT SDOUT DATT SDIN1 DATT SDIN2 SDIN3 - 2 - [AK4527B] RX1 RX2 RX3 RX4 XTI XTO DIR MCLK MCKO LRCK AK4112A LRCK BICK BICK DAUX SDTO LRCK AC3 SDOS BICK SDTO ...
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... AK4527BVQ AKD4527B n Pin Layout SDOS 1 I2C 2 SMUTE 3 BICK 4 LRCK 5 SDTI1 6 SDTI2 7 SDTI3 8 SDTO 9 DAUX 10 DFS 11 MS0056-E-00 -40 +85 C 44pin LQFP(0.8mm pitch) Evaluation Board for AK4527B AK4527BVQ Top View - 3 - [AK4527B] 33 DZF2/OVF 32 RIN+ 31 RIN- 30 LIN+ 29 LIN- 28 ROUT1 27 LOUT1 26 ROUT2 25 LOUT2 24 ROUT3 23 LOUT3 2000/10 ...
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... DEMA1-C0 default values are changed from “44.1kHz” to “OFF”. ICKS2-0 are removed. OVFE (Overflow detection enable) is added [AK4527B] AK4527B Available Auto setting Available (MCLK is fixed at auto setting mode; Normal: 512fs, Double: 256fs) Parallel/Serial mode Register only Available VCOM voltage AK4527B NC DZFE TST NC ADIF DZF2/OVF 2000/10 ...
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... Digital Ground Pin PDN I Power-Down & Reset Pin When “L”, the AK4527B is powered-down and the control registers are reset to default state. If the state of P/S or CAD0-1 changes, then the AK4527B must be reset by PDN. 18 TST I Test Pin This pin should be connected to DVSS. ...
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... The group 1 and 2 can be selected by DZFM2-0 bits if P/S = “L” and DZFE = “L”. 3. This pin becomes OVF pin if OVFE bit is set to “1” at serial control mode. 4. All input pins should not be left floating. MS0056-E-00 Function (Note 2) (Note bus control mode 2 C Bus Bus) (Note [AK4527B] 2000/10 ...
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... WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet. MS0056-E-00 ABSOLUTE MAXIMUM RATINGS Symbol min AVDD -0.3 DVDD -0.3 TVDD -0.3 (Note 6) - GND IIN - VINA -0.3 VIND -0.3 Ta -40 Tstg -65 Symbol min AVDD 4.5 DVDD 4.5 TVDD 2 [AK4527B] max Units 6.0 V 6.0 V 6 AVDD+0.3 V DVDD+0 150 C typ max Units 5.0 5.5 V 5.0 5.5 V 5.0 5.5 V ...
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... In the power-down mode. All digital input pins including clock pins (MCLK, BICK, LRCK) are held DVSS. MS0056-E-00 ANALOG CHARACTERISTICS min (Note 10) 2.85 (Note 11) 18 (Note 12 2.75 5 (Note 12) (Note 14) (Note 15 [AK4527B] typ max Units 24 Bits 102 102 dB 102 102 dB 110 dB 0.2 0 ppm/ C 3.0 3.15 Vpp ...
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... MS0056-E-00 FILTER CHARACTERISTICS Symbol min -0.005dB PB 0 -0.02dB - -0.06dB - -6.0dB - SB 24. -3dB FR -0.5dB -0.1dB -0.1dB PB 0 -6.0dB - SB 24 (Note 18 [AK4527B] typ max Units 19.76 kHz 20.02 - kHz 20.20 - kHz 22.05 - kHz kHz dB 0.005 dB 27.6 1/fs 0 µs 0.9 Hz 2.7 Hz 6.0 Hz 20.0 kHz 22.05 - kHz kHz dB 0.02 dB 21.9 ...
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... Duty 45 tBCK 160 tBCKL 65 tBCKH 65 (Note 19) tLRB 45 (Note 19) tBLR 45 tLRS tBSD tSDH 40 tSDS [AK4527B] typ max Units - - µA typ max Units 12.288 MHz ns ns 18.432 MHz ns ns 24.576 ...
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... PDN Pulse Width PDN “ ” to SDTO valid Notes: 20. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. 21. The AK4527B can be reset by bringing PDN “L” to “H” upon power-up. 22. These cycles are the number of LRCK rising from PDN rising ...
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... Timing Diagram MCLK LRCK BICK LRCK tBLR BICK tLRS SDTO SDTI MS0056-E-00 1/fCLK tCLKH tCLKL 1/fs tBCK tBCKH tBCKL Clock Timing tLRB tSDS tSDH Audio Interface Timing - 12 - [AK4527B] VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL tBSD 50%TVDD VIH VIL 2000/10 ...
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... MS0056-E-00 tCCKL tCCKH tCDS tCDH tHIGH tF tSU:DAT tSU:STA Start Bus mode Timing tPDV Power-down & Reset Timing - 13 - [AK4527B] VIH VIL VIH VIL VIH A4 VIL tCSW VIH VIL tCSH VIH VIL VIH VIL VIH VIL tSP VIH VIL tSU:STO ...
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... AK4527B may draw excess current because the device utilizes dynamic refreshed logic internally. If the external clocks are not present, the AK4527B should be in the power-down mode (PDN = “L” the reset mode (RSTN = “0”). After exiting reset at power-up etc., the AK4527B is in the power-down mode until MCLK and LRCK are input. ...
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... Table 5. System Clock Example (Auto Setting Mode) n De-emphasis Filter The AK4527B includes the digital de-emphasis filter (tc=50/15µs) by IIR filter. This filter corresponds to three sampling frequencies (32kHz, 44.1kHz, 48kHz). De-emphasis of each DAC can be set individually by register data of DEMA1-C0 (DAC1: DEMA1-0, DAC2: DEMB1-0, DAC3: DEMC1-0, see “Register Definitions”). ...
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... Don’t Care 23 22 Figure 3. Mode 2 Timing Don’t Care Lch Data Figure 4. Mode 3 Timing - 16 - [AK4527B Rch Data ...
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... OVF is “L” for 522/fs(=11.8ms@fs=44.1kHz) after PDN = “ ”, and then overflow detection is enabled. n Zero detection The AK4527B has two pins for zero detect flag outputs. Channel grouping can be selected by DZFM2-0 bits if P/S = “L” and DZFE = “L” (table 8). DZF1 pin corresponds to the group 1 channels and DZF2 pin corresponds to the group 2 channels. However DZF2 pin becomes OVF pin if OVFE bit is set to “ ...
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... ASAHI KASEI n Digital Attenuator AK4527B has channel-independent digital attenuator (256 levels, 0.5dB step). Attenuation level of each channel can be set by each ATT7-0 bits (table 10). ATT7-0 Table 10. Attenuation level of digital attenuator The transition between set values is soft transition of 7425 levels. It takes 7424/fs (168ms@fs=44.1kHz) from 00H(0dB) to FFH(MUTE). If PDN pin goes to “ ...
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... The AK4527B should be reset once by bringing PDN = “L” upon power-up. The AK4527B is powered up and the internal timing starts clocking by LRCK “ ” after exiting reset and power down state by MCLK. The AK4527B is in the power-down mode until MCLK and LRCK are input. ...
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... ASAHI KASEI n Power-Down The ADC and DACs of AK4527B are placed in the power-down mode by bringing PDN “L” and both digital filters are reset at the same time. PDN “L” also reset the control registers to their default values. In the power-down mode, the analog outputs go to VCOM voltage and DZF1-2 pins go to “ ...
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... There is a delay, 4~5/fs from RSTN bit “0” to the internal RSTN bit “0”. MS0056-E-00 4~5/fs (9) 1~2/fs (9) (1) 516/fs Digital Block Power-down Init Cycle Digital Block Power-down Normal Operation (2) GD (3) “0”data “0”data (2) GD (6) (5) (6) (7) Don’t care 4 5/fs (8) Figure 7. Reset sequence example - 21 - [AK4527B] Normal Operation GD (4) GD 2000/10 ...
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... ASAHI KASEI n Serial Control Interface The AK4527B can control its functions via registers. Internal registers may be written by 2 types of control mode. The chip address is determined by the state of the CAD0 and CAD1 inputs. PDN = “L” initializes the registers to their default values. Writing “0” to the RSTN bit can initialize the internal timing circuit. But in this case, the register data is not be initialized. When the state of P/S pin is changed, the AK4527B should be reset by PDN pin. * Writing to control register is invalid when PDN = “ ...
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... ATT4 ATT6 ATT5 ATT4 ATT6 ATT5 ATT4 ATT6 ATT5 ATT4 ATT6 ATT5 ATT4 0 0 DEMA1 DEMA0 DZFM2 DZFM1 - 23 - [AK4527B DIF1 DIF0 0 SMUTE SDOS DFS ACKS 0 ATT3 ATT2 ATT1 ATT0 ATT3 ATT2 ATT1 ATT0 ATT3 ATT2 ATT1 ATT0 ...
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... In this mode the input DAC data to SDTI2-3 is ignored. 11: N/A Register bit of LOOP1 is ORed with LOOP1 pin if P/S = “L”. MS0056-E- LOOP1 LOOP0 [AK4527B DIF1 DIF0 0 SMUTE SDOS DFS ACKS 2000/10 ...
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... ATT7 ATT6 ATT5 ATT4 ATT7 ATT6 ATT5 ATT4 DEMA1 DEMA0 [AK4527B ATT3 ATT2 ATT1 ATT0 ATT3 ATT2 ATT1 ATT0 ATT3 ATT2 ATT1 ATT0 ATT3 ATT2 ATT1 ATT0 ATT3 ATT2 ATT1 ATT0 ATT3 ...
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... OVFE: Overflow detection enable 0: Disable, pin#33 becomes DZF2 pin. 1: Enable, pin#33 becomes OVF pin. MS0056-E- DZFM2 DZFM1 DZFM0 [AK4527B RSTN PWVRN PWADN PWDAN 2000/10 ...
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... Digital Ground Analog Ground MS0056-E-00 SYSTEM DESIGN Analog 5V + 10u 2.2u + 0.1u 0.1u DZF2 33 RIN+ RIN- LIN+ AK4527B LIN- ROUT1 LOUT1 ROUT2 LOUT2 ROUT3 LOUT3 0.1u 10u + 5 Figure 10. Typical Connection Diagram - 27 - [AK4527B] 470 32 1n 470 31 470 30 1n 470 29 28 MUTE 27 MUTE 26 MUTE 25 MUTE 24 MUTE 23 MUTE 2000/10 ...
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... The ideal code is 000000H(@24bit) with no input signal. The DC offset is removed by the internal HPF. The AK4527B samples the analog inputs at 64fs. The digital filter rejects noise above the stop band except for multiples of 64fs. A simple RC filter (fc=150kHz) may be used to attenuate any noise around 64fs and most audio signals do not have significant energy at 64fs ...
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... Same circuit 4.7k 10k Vop 10k - 470 - + + NJM2100 470 Vop=AVDD=5V Same circuit AVDD 10k +Vop 10k - - + + NJM5532 -Vop Vop=12V - 29 - [AK4527B] 3.0Vpp 22µ 10k Signal AVDD 6.4Vpp 4.7k 0.1µ BIAS + 4.7k 10µ 22µ 10k Signal AVDD 3.2Vpp 4.7k 0.1µ BIAS + 4.7k 10µ 4.7k 22µ 10k Signal AVDD 3 ...
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... DC offsets on analog outputs are eliminated by AC coupling since DAC outputs have DC offsets of a few mV. n Peripheral I/F Example The AK4527B can accept the signal of device with a nominal 3.3V supply because of TTL input. The power supply for output buffer (TVDD) of the AK4527B should be 3.3V when the peripheral devices operate at a nominal 3.3V supply. ...
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... LRCK SDWCK0 BICK SDBCK0 MCLK YSS912 256fs MCKO1 LRCK YM3436 BICK or AK4112A SDTO SDIA0 RX SDTO SDI1 SDTI1 SDO0 SDTI2 SDO1 AK4527B SDTI3 SDO2 LRCK FSR BICK SCKR MCLK FST SCKT 256fs MCKO1 DSP56362 LRCK BICK AK4112A SDTO SDI0 [AK4527B] 2000/10 ...
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... ASAHI KASEI 44pin LQFP (Unit: mm) 12.80 0.30 10. 0.37 0.10 0.15 n Package & Lead frame material Package molding compound: Lead frame material: Lead frame surface treatment: MS0056-E-00 PACKAGE 1.70max 0.60 0.20 Epoxy Cu Solder plate - 32 - [AK4527B] 0 0.2 0.17 0.05 2000/10 ...
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... AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0056-E-00 MARKING AKM AK4527BVQ XXXXXXX JAPAN 1 1) Pin #1 indication 2) Date Code: XXXXXXX(7 digits) 3) Marking Code: AK4527BVQ 4) Country of Origin 5) Asahi Kasei Logo IMPORTANT NOTICE - 33 - [AK4527B] 2000/10 ...