ak4529 AKM Semiconductor, Inc., ak4529 Datasheet
ak4529
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ak4529 Summary of contents
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... ADC for passing audio data to the primary audio output port. Control may be set directly by pins or programmed through a separate serial interface. The AK4529 has a dynamic range of 102dB for ADC, 106dB for DAC and is well suited for digital surround for home theater and car audio. An AC-3 system can be built with a IEC60958(SPDIF) receiver such as the AK4112A ...
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... HPF HPF DATT MCLK LRCK BICK DATT DATT Format Converter DATT SDOUT DATT SDIN1 DATT SDIN2 SDIN3 SDIN4 DATT DATT - 2 - [AK4529] RX1 RX2 RX3 RX4 XTI XTO DIR MCLK MCKO LRCK AK4112A LRCK BICK BICK DAUX SDTO LRCK AC3 SDOS BICK ...
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... AK4529VQ AKD4529 n Pin Layout SDOS 1 I2C 2 SMUTE 3 BICK 4 LRCK 5 SDTI1 6 SDTI2 7 SDTI3 8 SDTO 9 DAUX 10 DFS 11 MS0082-E-00 -40 +85 C 44pin LQFP(0.8mm pitch) Evaluation Board for AK4529 AK4529VQ Top View - 3 - [AK4529] 33 DZF2/OVF 32 RIN 31 LIN ROUT1 27 LOUT1 26 ROUT2 25 LOUT2 24 ROUT3 23 LOUT3 2001/3 ...
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... ATS1-0 (DATT transition time) are added. DZFM3 (Zero detection mode) is added. ATT7-0 (LOUT4 output volume control) are added. ATT7-0 (ROUT4 output volume control) are added [AK4529] AK4529 8ch Single-ended input 7424/fs, 1024/fs or 256/fs Available Available AK4529 SDTI4 CAD1 CAD0 LOUT4 ROUT4 NC NC LIN RIN TDM 2001/3 ...
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... Digital Ground Pin PDN I Power-Down & Reset Pin When “L”, the AK4529 is powered-down and the control registers are reset to default state. If the state of P/S or CAD0-1 changes, then the AK4529 must be reset by PDN. 18 TST I Test Pin This pin should be connected to DVSS. ...
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... The group 1 and 2 can be selected by DZFM3-0 bits if P/S = “L” and DZFE = “L”. 3. This pin becomes OVF pin if OVFE bit is set to “1” at serial control mode. 4. All input pins should not be left floating. MS0082-E-00 Function (Note 2) (Note bus control mode 2 C Bus Bus [AK4529] 2001/3 ...
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... WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet. MS0082-E-00 ABSOLUTE MAXIMUM RATINGS Symbol min AVDD -0.3 DVDD -0.3 TVDD -0.3 (Note 6) - GND IIN - VINA -0.3 VIND -0.3 Ta -40 Tstg -65 Symbol min AVDD 4.5 DVDD 4.5 TVDD 2 [AK4529] max Units 6.0 V 6.0 V 6 AVDD+0.3 V DVDD+0 150 C typ max Units 5.0 5.5 V 5.0 5.5 V 5.0 5.5 V ...
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... In the power-down mode. All digital input pins including clock pins (MCLK, BICK, LRCK) are held DVSS. MS0082-E-00 ANALOG CHARACTERISTICS min 2.90 AIN=0.65xVREFH 3.05 (Note 9) 15 (Note 10 2.75 5 (Note 10) (Note 12) (Note 13 [AK4529] typ max Units 24 Bits 102 102 dB 102 102 dB 110 dB 0.2 0 ppm/ C 3.10 3.30 Vpp 3.25 3 ...
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... SB 24 (Note 16) DC CHARACTERISTICS Symbol min VIH 2.2 VIL - Iout=-100µA) VOH TVDD-0.5 Iout=-100µA) VOH AVDD-0.5 VOL - Iout= 3mA) VOL - Iin - - 9 - [AK4529] typ max Units 19.76 kHz 20.02 - kHz 20.20 - kHz 22.05 - kHz kHz dB 0.005 dB 27.6 1/fs 0 µs 0.9 Hz 2.7 Hz 6.0 Hz 20.0 kHz 22.05 - kHz ...
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... Units 12.288 MHz ns ns 18.432 MHz ns ns 24.576 MHz kHz 96 kHz kHz ...
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... PDN Pulse Width PDN “ ” to SDTO valid Notes: 18. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. 19. The AK4529 can be reset by bringing PDN “L” to “H” upon power-up. 20. These cycles are the number of LRCK rising from PDN rising ...
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... MS0082-E-00 1/fCLK tCLKH tCLKL 1/fsn, 1/fsd tBCK tBCKH tBCKL Clock Timing (TDM= “0”) 1/fCLK tCLKH tCLKL 1/fs tLRH tLRL tBCK tBCKH tBCKL Clock Timing (TDM= “1” [AK4529] VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL 2001/3 ...
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... SDTI LRCK tBLR BICK SDTO SDTI MS0082-E-00 tLRB tSDS tSDH Audio Interface Timing (TDM= “0”) tLRB tSDS tSDH Audio Interface Timing (TDM= “1” [AK4529] VIH VIL VIH VIL tBSD 50%TVDD VIH VIL VIH VIL VIH VIL tBSD 50%TVDD VIH ...
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... MS0082-E-00 tCCKL tCCKH tCDS tCDH tHIGH tF tSU:DAT tSU:STA Start Bus mode Timing tPDV Power-down & Reset Timing - 14 - [AK4529] VIH VIL VIH VIL VIH A4 VIL tCSW VIH VIL tCSH VIH VIL VIH VIL VIH VIL tSP VIH VIL tSU:STO ...
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... If the external clocks are not present, the AK4529 should be in the power-down mode (PDN = “L” the reset mode (RSTN = “0”). After exiting reset at power-up etc., the AK4529 is in the power-down mode until MCLK and LRCK are input. ...
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... Table 5. System Clock Example (Auto Setting Mode) n De-emphasis Filter The AK4529 includes the digital de-emphasis filter (tc=50/15µs) by IIR filter. This filter corresponds to three sampling frequencies (32kHz, 44.1kHz, 48kHz). De-emphasis of each DAC can be set individually by register data of DEMA1-C0 (DAC1: DEMA1-0, DAC2: DEMB1-0, DAC3: DEMC1-0, see “Register Definitions”). ...
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... SDTI1 24bit, Left justified 20bit, Right justified 24bit, Left justified 24bit, Right justified 24bit, Left justified 24bit, Left justified 2 2 24bit 24bit Table 8. Audio data formats (TDM format [AK4529] LRCK BICK H/L 48fs H/L 48fs H/L 48fs Default L/H 48fs Sync BICK 256fs ...
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... Don’t Care 23 22 Figure 3. Mode 2 Timing Don’t Care Lch Data Figure 4. Mode 3 Timing - 18 - [AK4529 Rch Data ...
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... BICK Figure 7. Mode 6 Timing 256 BICK 23 0 Rch 32 BICK BICK 32 BICK 32 BICK 32 BICK 32 BICK Figure 8. Mode 7 Timing - 19 - [AK4529 BICK 32 BICK BICK 32 BICK ...
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... ASAHI KASEI n Overflow Detection The AK4529 has overflow detect function for analog input. Overflow detect function is enable if OVFE bit is set to “1” at serial control mode. OVF pin goes to “H” if analog input of Lch or Rch overflows (more than -0.3dBFS). OVF output for overflowed analog input has the same group delay as ADC (GD = 27.6/fs = 626µ ...
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... ASAHI KASEI n Digital Attenuator AK4529 has channel-independent digital attenuator (256 levels, 0.5dB step). Attenuation level of each channel can be set by each ATT7-0 bits (table 11). ATT7-0 Table 11. Attenuation level of digital attenuator Transition time between set values of ATT7-0 bits can be selected by ATS1-0 bits (table 12). ...
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... The AK4529 should be reset once by bringing PDN = “L” upon power-up. The AK4529 is powered up and the internal timing starts clocking by LRCK “ ” after exiting reset and power down state by MCLK. The AK4529 is in the power- down mode until MCLK and LRCK are input. ...
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... ASAHI KASEI n Power-Down The ADC and DACs of AK4529 are placed in the power-down mode by bringing PDN “L” and both digital filters are reset at the same time. PDN “L” also reset the control registers to their default values. In the power-down mode, the analog outputs go to VCOM voltage and DZF1-2 pins go to “ ...
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... There is a delay, 4~5/fs from RSTN bit “0” to the internal RSTN bit “0”. MS0082-E-00 4~5/fs (9) 1~2/fs (9) (1) 516/fs Digital Block Power-down Init Cycle Digital Block Power-down Normal Operation (2) GD (3) “0”data “0”data (2) GD (6) (5) (6) (7) Don’t care 4 5/fs (8) Figure 11. Reset sequence example - 24 - [AK4529] Normal Operation GD (4) GD 2001/3 ...
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... ASAHI KASEI n Serial Control Interface The AK4529 can control its functions via registers. Internal registers may be written by 2 types of control mode. The chip address is determined by the state of the CAD0 and CAD1 inputs. PDN = “L” initializes the registers to their default values. Writing “0” to the RSTN bit can initialize the internal timing circuit. But in this case, the register data is not be initialized. When the state of P/S pin is changed, the AK4529 should be reset by PDN pin. * Writing to control register is invalid when PDN = “ ...
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... CAD1 and CAD0 (device address bits). These two bits identify the specific device on the bus. The hard- wired input pins (CAD1 pin and CAD0 pin) set them. If the slave address match that of the AK4529 and R/W bit is “0”, the AK4529 generates the acknowledge and the write operation is executed. If R/W bit is “1”, the AK4529 generates the not acknowledge since the AK4529 can be only a slave-receiver ...
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... MASTER S START CONDITION SDA SCL MS0082-E-00 Figure 17. START and STOP conditions Figure 18. Acknowledge on the I C-bus data line change stable; of data data valid allowed 2 Figure 19. Bit transfer on the I C-bus - 27 - [AK4529] P stop condition not acknowledge acknowledge 8 9 clock pulse for acknowledgement 2001/3 ...
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... ATT6 ATT5 ATT4 ATT6 ATT5 ATT4 DEMD0 DEMA1 DEMA0 0 0 ATS1 ATS0 DZFM3 DZFM2 DZFM1 ATT6 ATT5 ATT4 ATT6 ATT5 ATT4 - 28 - [AK4529 DIF1 DIF0 0 SMUTE SDOS DFS ACKS 0 ATT3 ATT2 ATT1 ATT0 ATT3 ATT2 ATT1 ATT0 ATT3 ATT2 ATT1 ...
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... TDM: TDM Format Select 0: Normal format 1: TDM format Register bit of TDM is ORed with the TDM pin if P/S = “L”. TDM pin should be “H” if TDM mode is used. MS0082-E- TDM [AK4529 DIF1 DIF0 0 SMUTE 2001/3 ...
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... SDTI2(L), SDTI3(L), SDTI4(L) SDTI1(R) SDTI2(R), SDTI3(R), SDTI4(R) In this mode the input DAC data to SDTI2-4 is ignored. 11: N/A LOOP1-0 should be set to “00” at TDM bit “1”. MS0082-E- LOOP1 LOOP0 [AK4529 SDOS DFS ACKS 2001/3 ...
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... ATT7 ATT6 ATT5 ATT4 ATT7 ATT6 ATT5 ATT4 DEMD1 DEMD0 DEMA1 DEMA0 [AK4529 ATT3 ATT2 ATT1 ATT0 ATT3 ATT2 ATT1 ATT0 ATT3 ATT2 ATT1 ATT0 ATT3 ATT2 ATT1 ATT0 ATT3 ATT2 ATT1 ATT0 ...
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... Disable, pin#33 becomes DZF2 pin. 1: Enable, pin#33 becomes OVF pin. MS0082-E- ATS1 ATS0 DZFM3 DZFM2 DZFM1 DZFM0 [AK4529 RSTN PWVRN PWADN PWDAN 2001/3 ...
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... DAUX 11 DFS Power-down control Digital Ground Analog Ground MS0082-E-00 SYSTEM DESIGN Analog 5V + 10u 2.2u + 0.1u 0.1u DZF2 33 RIN LIN NC NC AK4529 ROUT1 LOUT1 ROUT2 LOUT2 ROUT3 LOUT3 0.1u 10u + 5 Figure 20. Typical Connection Diagram - 33 - [AK4529 MUTE 27 MUTE 26 MUTE 25 MUTE 24 MUTE 23 MUTE MUTE MUTE 2001/3 ...
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... VREFH Vpp (typ)@fs=44.1kHz. The ADC output data format 2’s compliment. The DC offset is removed by the internal HPF. The AK4529 samples the analog inputs at 64fs. The digital filter rejects noise above the stop band except for multiples of 64fs. The AK4529 includes an anti-aliasing filter (RC filter) to attenuate a noise around 64fs. ...
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... DC offsets on analog outputs are eliminated by AC coupling since DAC outputs have DC offsets of a few mV. n Peripheral I/F Example The AK4529 can accept the signal of device with a nominal 3.3V supply because of TTL input. The power supply for output buffer (TVDD) of the AK4529 should be 3.3V when the peripheral devices operate at a nominal 3.3V supply. ...
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... SDOB1 SDTI3 SDOB2 SDTI4 SDOB3 MCLK MCKO BICK BICK AK4112A LRCK LRCK SDTO ACI AK4529 SCKR FSR SDI0 SDTO SDI1 DSP56362 SCKT FST SDTI1 SDO0 SDTI2 SDO1 SDTI3 SDO2 SDTI4 SDO3 - 36 - [AK4529] Digital Input RX Digital Input 256fs RX Digital Input 256fs 2001/3 ...
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... ASAHI KASEI 44pin LQFP (Unit: mm) 12.80 0.30 10. 0.37 0.10 0.15 n Package & Lead frame material Package molding compound: Lead frame material: Lead frame surface treatment: MS0082-E-00 PACKAGE 1.70max 0.60 0.20 Epoxy Cu Solder plate - 37 - [AK4529] 0 0.2 0.17 0.05 2001/3 ...
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... AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0082-E-00 MARKING AK4529VQ XXXXXXX 1 1) Pin #1 indication 2) Date Code: XXXXXXX(7 digits) 3) Marking Code: AK4529VQ 4) Asahi Kasei Logo IMPORTANT NOTICE - 38 - [AK4529] 2001/3 ...