ak4525 AKM Semiconductor, Inc., ak4525 Datasheet - Page 13

• Manufacturer Part Number: ak4525
• Description: 20bit Stereo ?? Adc & Dac With X? Tal Osc
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
n Power-Down & Reset
The ADC and DAC of AK4525 are placed in the power-down mode by bringing a power down pin, PDN “L” and each
digital filter is also reset at the same time.This reset should always be done after power-up. In case of the ADC, an analog
initialization cycle starts after exiting the power-down mode. Therefore, the output data, SDTO becomes available after
516 cycles of LRCK clock. This initialization cycle does not affect the DAC operation. Figure 7 shows the power-up
sequence.
During the power-down mode, the crystal oscillator is left running. The condition of the outputs are as follows.
MS0053-E-00
(1) The analog part of ADC is initialized after exiting the power-down state.
(2) Digital output corresponding to analog input and analog output corresponding to digital input have the group delay
(3) ADC output is “0” data at the power-down state.
(4) Small click noise occurs at the end of initialization of the analog part. Please mute the digital output externally if
(5) Click noise occurs at the edge of PDN.
(6) Please mute the analog output externally if the click noise (5) influences system application.
(GD).
the click noise influences system application.
SDTO = “L”
MCKO = Clock out
LRCK = “H” (master mode)
SCLK = “L” (master mode)
AOUT = VCOM (VA/2)
Clock In
MCLK,LRCK,SCLK
DAC Internal
DAC In
DAC Out
ADC Internal
ADC In
ADC Out
External
PDN
(Digital)
(Analog)
(Analog)
(Digital)
Mute
State
State
Normal Operation
Normal Operation
(6)
GD
GD
(2)
(2)
Figure 7. Power-up Sequence
(5)
Power-down
Power-down
Mute ON
“0”data
“0”data
The clocks may be stopped.
(3)
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(5)
Normal Operation
Init Cycle
516/fs
(1)
GD
(4)
Normal Operation
GD
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