ak4523 AKM Semiconductor, Inc., ak4523 Datasheet - Page 14

• Manufacturer Part Number: ak4523
• Description: 20bit Stereo Ds Adc & Dac
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
n Power-Down & Reset
The ADC and DAC of AK4523 are placed in the power-down mode by bringing a power down pin, PD “L” and each
digital filter is also reset at the same time.This reset should always be done after power-up. In case of the ADC, an analog
initialization cycle starts after exiting the power-down mode. Therefore, the output data, SDTO becomes available after
516 cycles of LRCK clock. This initialization cycle does not affect the DAC operation. Figure 6 shows the power-up
sequence.
M0021-E-03
(1) The analog part of ADC is initialized after exiting the power-down state.
(2) Digital output corresponding to analog input and analog output corresponding to digital input have the group delay
(3) ADC output is “0” data at the power-down state.
(4) Small click noise occurs at the end of initialization of the analog part. Please mute the digital output externally if the
(5) Click noise occurs at the edge of PD .
(6) Please mute the analog output externally if the click noise (5) influences system application.
(GD).
click noise influences system application.
DAC Internal
DAC In
DAC Out
Clock In
MCLK,LRCK,SCLK
ADC Internal
ADC In
ADC Out
External
(Digital)
(Analog)
(Analog)
(Digital)
Mute
PD
State
State
Normal Operation
Normal Operation
(6)
GD
GD
(2)
(2)
Figure 6. Power-up sequence
(5)
Power-down
Power-down
Mute ON
“0”data
“0”data
The clocks may be stopped.
(3)
- 14 -
(5)
Normal Operation
Init Cycle
516/fs
(1)
GD
(4)
Normal Operation
GD
[AK4523]
1999/12