ak4522 AKM Semiconductor, Inc., ak4522 Datasheet - Page 12

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ak4522

Manufacturer Part Number
ak4522
Description
20bit Stereo ?? Adc & Dac
Manufacturer
AKM Semiconductor, Inc.
Datasheet

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ASAHI KASEI
n Power-Down & Reset
The ADC and DAC of AK4522 are placed in the reset mode by bringing a reset pin, PD “L”. This reset should always
be done after power-up. In case of the ADC, an analog initialization cycle starts after exiting the reset mode. Therefore,
the output data, SDTO becomes available after 516 cycles of LRCK clock. This initialization cycle does not affect the
DAC operation. Figure 6 shows the power-up sequence.
M0020-E-01
(1) The analog part of ADC is initialized after exiting the reset state.
(2) Digital output corresponding to analog input and analog output corresponding to digital input have the group delay
(3) A/D output is “0” data at the reset state.
(4) Small click noise occurs at the end of initialization of the analog part. Please mute the digital output externally if
(5) Click noise occurs at the edge of PD .
(6) Please mute the analog output externally if the click noise (5) influences system application.
(GD).
the click noise influences system application.
Clock In
MCLK,LRCK,SCLK
DAC Internal
DAC In
DAC Out
ADC Internal
ADC In
ADC Out
External
(Digital)
(Analog)
(Analog)
(Digital)
Mute
PD
State
State
Normal Operation
Normal Operation
(6)
GD
GD
(2)
(2)
Figure 6. Power-up sequence
(5)
Mute ON
“0”data
“0”data
Reset
Reset
The clocks may be stopped.
(3)
- 12 -
(5)
Normal Operation
Init Cycle
516/fs
(1)
GD
(4)
Normal Operation
GD
[AK4522]
1998/10

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