ak4564 AKM Semiconductor, Inc., ak4564 Datasheet
ak4564
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ak4564 Summary of contents
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... AK4564 has new recording features, a digital equalizer for microphone inputs and a digital ALC (Automatic Level Control). The playback features also include LINEOUT-Amp, digital volume, Headphone-Amp and Speaker-Amp. The AK4564 suits a portable application with a built-in LCD and etc. The AK4564 is housed in a space-saving 48pin LQFP package. ...
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... SPK Power Management BEEP2 MS0140-E-01 LIN1 LIN2 BEEP1 RIN2 ADC EQ LPF HPF ADC AOUTP2 ALC2 +2dBV MIX LOUT2 ROUT2 Figure 1. AK4564 block diagram - 2 - RIN1 Pre-Amp MIC Audio I/F Controller ALC1 DAC DAC OATT AOUTP1 +2dBV Control Register I/F CSN CCLK CDTI LOUT1 ROUT1 ...
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... RIN2 I Rch Line #2 Input Pin DAC Block 18 LOUT1 O Lch Line #1 Output Pin 20 ROUT1 O Rch Line #1 Output Pin 22 LOUT2 O Lch Line #2 Output Pin 24 ROUT2 O Rch Line #2 Output Pin NOTE: All digital input pins must not be left floating. MS0140-E-01 PIN/FUNCTION FUNCTION - 3 - [AK4564] 2002/07 ...
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No. Pin Name I/O Headphone Amp 26 HPL O Lch Headphone Amp Output Pin 27 HPR O Rch Headphone Amp Output Pin 29 MUTET O Headphone Amp MUTE Capacitor Pin Speaker Amp Block 1 SP0 O Speaker Amp positive Output ...
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... ASAHI KASEI n Ordering Guide AK4564VQ -20 +85 C AKD4564 Evaluation board for AK4564 n Pin layout SP0 1 MUTE 2 SP1 3 PDN 4 SVDD 5 SVSS 6 BCLK 7 MCLK 8 LRCK 9 CDTI 10 CSN 11 CCLK 12 MS0140-E-01 48pin LQFP (0.5mm pitch) 36 BEEP1 35 MIN 34 MOUT 33 VCOM AK4564 32 AVDD 31 AVSS 30 HVCM Top View 29 MUTET ...
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... AKM assumes no responsibility for the usage beyond the conditions in this datasheet. MS0140-E-01 ABSOLUTE MAXIMUM RATING Symbol AVDD HVDD MVDD DVDD SVDD GND1 GND2 GND3 IIN VINA1 VINA2 VIND Ta Tstg Pd1 Pd2 Symbol min AVDD 2.6 HVDD 2.6 MVDD 2.6 or “AVDD – 0.1” DVDD 2.6 SVDD 2 [AK4564] min max Units -0.3 6.0 V -0.3 6.0 V -0.3 6.0 V -0.3 6.0 V -0 -0.3 AVDD+0 ...
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... Note 18. Input from INTL, INTR, EXTL or EXTR pins. Pre-Amp Gain = + 23.9dB, PRE = “1”, IVOL = +0dB External resistor of Pre-Amp is “Rf = 10k , Ri = 680 ”. (Refer to Figure 12) * 0dBV = 1Vrms = 2.83Vpp MS0140-E-01 ANALOG CHARACTERISTICS 20kHz, unless otherwise specified) min 70 +18 3 1.4 70 -5.1 -58 [AK4564] typ Max Units 100 130 k -4.5 dBV +24 + 1.6 1 bits ...
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... L =100 L 22 100 - the output voltage is (0.59 x AVDD) Vpp 100 , the output voltage is (0.98 x AVDD) L HPL, HPR Oscillation prevention circuit Figure 2. Headphone-Amp Output Circuit - 8 - [AK4564] typ max Units 16 bits +2.8 dBV 100 dB 0 -4.7 -3.9 dBV -0 ...
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... Note 27. In power-down, all digital input pins including clock (MCLK, BCLK and LRCK) pins are held at “DVDD” or “DVSS”. PDN pin is held at “DVSS”. * 0dBV = 1Vrms = 2.83Vpp MS0140-E-01 min typ 14 23 -5.3 -4 4.5 6.5 6.5 7.5 5.5 2 [AK4564] max Units -4.5 dBV 33 k -3.7 dBV -4.5 dBV 26 k -4.5 dBV 26 k 19 ...
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... For DAC, this time is from setting the 16bit data of both channels on input register to the output of analog signal. Note 30. DAC à LOUT1/ROUT1, LOUT2/ROUT2 MS0140-E-01 FILTER CHARACTERISTICS Symbol min 29 26 [AK4564] typ max Units 18.9 kHz 21.8 - kHz 23.0 - kHz kHz dB 0.1 dB 19 21.7 kHz 24.0 - ...
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C; AVDD, DVDD, SVDD=2.6 3.6V, MVDD, HVDD=2.6 5.5V) Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage Iout=-200 A Low-Level Output Voltage Iout=200 A Input Leakage Current (Ta=25 C; AVDD, DVDD, SVDD=2.6 3.6V, MVDD, HVDD=2.6 5.5V; C Parameter ...
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Timing Diagram MCLK tCLKH LRCK BCLK tBLKH LRCK tBLR BCLK tLRM SDTO D0 (LSB) SDTI Figure 4. Audio Data Input/Output Timing (Audio I/F format: No. 0) MS0140-E-01 1/fCLK tCLKL 1/fs tBLK tBLKL Figure 3. Clock Timing tLRB tBSD D15 ...
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... ASAHI KASEI CSN tCSS CCLK CDTI CSN CCLK CDTI D3 PDN SDTO MS0140-E-01 tCCKL tCCKH tCDS tCDH op2 op1 0 Figure 5. WRITE Command Input Timing D2 D1 Figure 6. WRITE Data Input Timing tPDW tPDV Figure 7. Reset Timing - 13 - [AK4564] 1.5V 0.6V 1.5V 0.6V 1.5V 0.6V op0 A4 tCSW 1.5V 0.6V tCSH 1.5V 0.6V 1.5V D0 0.6V 0.6V 50%DVDD 2002/07 ...
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... If the external clocks are not present, the AK4564 should be placed in MIC = ADC = DAC = VCOM = HPP = SPKP = AOUT1P = AOUT2P = “0” or PDN = “L”. However, ADC, DAC and ALC2 are in power-down mode until MCLK, BCLK and LRCK is input, even if they release a power-down mode by PDN pin or control register. (Refer to the “ ...
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... Figure 8. Audio Data Timing (No. Don’t Care Figure 9. Audio Data Timing (No. [AK4564] BCLK Figure Figure 8 RESET 32fs = 64fs Figure 9 Figure 10 32fs 32fs Figure ...
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... Don’t Care Lch Data Figure 11. Audio Data Timing (No. [AK4564 ...
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... V at MVDD=4.5V. When the output current is 3mA, the output voltage is typically (MVDD – 1. MVDD=2.8V and typically (MVDD – 1. MVDD=4.5V. When MIC bit is “0”, the output current is not supplied. MS0140-E-01 100pF(C2 Pre-Amp Figure 12. Pre-Amp - 17 - [AK4564] 2002/07 ...
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... MIX1-Amp is powered-up when ADC bit = “1” or MIX1P bit = “0”. 4. MIX2-Amp MIX2-Amp mixes Pre-Amp output and MIX1-Amp output at the ratio of “1:1”. MS0140-E-01 To Rch MIX1 typ.100k typ.100k AIN1, AIN2 or BEEP1 BEEP1 typ.100k - AIN1 + PRE typ.100k MIX1 AIN2 From Pre-Amp 30% . (Refer to Figure 13 [AK4564 ADC + MIX2 To HP-Amp 2002/07 ...
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... LIN1/RIN1 and LIN2/RIN2 pins are non-inverted and output from ADC. 6. MONO Mode When MONO bit is “1”, the recording blocks in the AK4564 becomes MONO mode. The Pre-Amp, MIX1-Amp, MIX2-Amp and ADC analog block of the right channel are powered-down. And the right channel data of ADC is the same as the left channel data of ADC. When changing MONO mode, the ADC should be powered-up by changing ADC bit = “ ...
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... When PDN pin changes from “L” to “H” after power-up, LINEOUT-Amps become Power-Save-Mode. In Power-Save-Mode, LOUT1/ROUT1 (LOUT2/ROUT2) pins gradually become HVCM voltage via an internal resistor (typ.200k ) from Hi-Z to decrease a pop noise. When Power OFF, the pop noise can be decreased by using Power-Save-Mode. MS0140-E- [AK4564] 2002/07 ...
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Headphone-Amps The Power supply voltage for Headphone-Amp is supplied from HVDD pin and centered around HVCM voltage. The load resistance and output voltage are specified by HVDD voltage. The output voltage can be changed by supplying AVDD voltage and ...
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Headphone-Amps are powered-up/down by HPP bit. When HPP bit is “0”, Headphone-Amps are powered-down and HPL and HPR pins are fixed to “L” (AVSS). At power-up/down, the common voltage of HPL/HPR pin is settled by a constant which determined by ...
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... ASAHI KASEI Headphone-Amps of the AK4564 has a possibility of oscillation depending on headphone characteristics. Therefore, Headphone-amp oscillation prevention circuit may be needed. Headphone-Amps oscillation prevention circuit example is shown in Figure 18. HP-Amp - + Figure 18. Headphone-Amp oscillation prevention circuit example * When Headphone-Amp and Speaker-Amp are powered-up at the same time, refer to the condition of “ ...
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SPEAKER BLOCK The output signal from DAC is converted into a mono signal, [(L+R)/2], and is supplied to Speaker-Amp via ALC2 circuit. This Speaker-Amp has a monaural output by BTL, which can be output up to 80mW at 8 ...
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... BEEP2S bit From BEEP2 ALCS bit From ALC2 Figure 20. Speaker-Amp Internal equivalent circuit MS0140-E-01 FS-2dB = -6.5dBV -4.5dBV -2dB +6dB -12.75dBV -1.4dB +9.75dB -16.5dBV FS-4dB = -8.5dBV +18dB -24.75dBV ALC2 SPK-AMP - + - + - 25 - [AK4564] +4.6dB 0dBV -1.9dBV Full-differential Single-ended -7.9dBV -10dBV -20dBV -30dBV SP1 8 SP0 2002/07 ...
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... ASAHI KASEI n Digital EQ/HPF/LPF Circuits The AK4564 performs equalizing, filtering and ALC (Automatic Level Control) by digital domain for A/D converter data. The equalizing circuit emphasizes stereo separation when using internal microphone. LPF1, LPF2 and HPF2 are IIR st filters of 1 order to compensate frequency response of microphone and etc. HPF3 is IIR filter of 2 wind-noise. Refer to the section of “ ...
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... Writing to IVOL register when ALC1 is OFF When writing control register continuously, the change of IVOL should be written after zero crossing timeout. If IVOL is changed by writing to control register before zero crossing detection, IVOL value of L/R channels may not give a difference level. MS0140-E-01 Output Signal < ALC1 limiter detection level - 27 - [AK4564] 2002/07 ...
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... When ALC1 bit changes into “0”, it takes a period set by ZTM1-0 bit to return manual mode. MS0140-E-01 Manual Mode WR (ZTM1-0, WTM1-0) WR (REF7-0) *1: The value of IVOL should be WR (IVOL7-0) the same or smaller than REF’s WR (ALC1= “1”) ALC1 Operation Finish ALC1 mode? Yes WR (ALC1= “0” [AK4564] 2002/07 ...
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... The FADEIN operation is done until the limiter detection level (LMTH1-0) or the reference level (REF7-0). After completing the FADEIN operation. The FADEIN operation is completed and the ALC1 operation starts. (5) FADEIN time is set by REF7-0, FDTM1-0, FSTM and FDATT bits e.g. REF7-0 = E1H(225 dec), FDTM1-0 = 40ms, FDATT1 step (225 x FDTM1-0) / FDATT1-0 = 225 x 40ms /2 = 4.5s MS0140-E-01 (5) (1) (2) (3) ( [AK4564] 2002/07 ...
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... WR (IVOL = XXH): The IVOL value should be set to the same or smaller than REF’s. (7) WR (ALC1 = “1”, FDOUT = “0”): The ALC1 operation restarts. But the ALC1 bit should be written until completing zero crossing detection operation of IVOL. (8) Release an external mute function for analog and digital outputs. MS0140-E-01 (2) (1) (3) (4) (5) ( [AK4564] (7) (8) 2002/07 ...
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... CSN 0 1 CCLK CDTI op2 op1 “1” “0” op2-op0: Op code (101:WRITE) A4-A0: D7-D0: MS0140-E- op0 “1” Register Address Control data Figure 25. Control Data Timing - 31 - [AK4564] 2002/07 ...
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... FDTM0 0 GSEL FDATT1 FDATT0 RGAIN1 RGAIN0 LMAT1 LMAT0 0 FSTM 0 0 REF6 REF5 REF4 IVOL6 IVOL5 IVOL4 0 0 MIX1P MONO ZCE OATT6 OATT5 OATT4 Table 5. AK4564 Register Map HPMIX HPG BEEP1 [AK4564 AIN2 AIN1 PRE INT/EXT ...
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... OFF (Default SPPS: Speaker-Amp Power-Save-Mode 0: Power-Save-Mode (Default) 1: Normal operation When SPPS bit = “0”, SP0 pin becomes Hi-Z and SP1 pin is generated to SVDD/2 voltage. MS0140-E- ALCS BEEP2H BEEP2S AOUT2 AOUT1 [AK4564 MOUT HPDAC 2002/07 ...
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... VCOM bit must go “1” before each block operates. Except the case of MIC=ADC=DAC=VCOM=HPP=SPKP=AOUT1P=AOUT2P = “0” or PDN pin = “L”, MCLK, BCLK and LRCK should not be stopped. MS0140-E- SPKP HPP [AK4564 VCOM DAC ADC MIC 2002/07 ...
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... MOUT BEEP2 AOUT2 ALC2 *1 D7:AOUT2P D6:AOUT1P Figure 26. Power Management Control Input Selector AVDD BEEP2 AOUT2 AOUT1 ALC2 AVDD HVDD - 35 - [AK4564] ADC ALC1 VCOM HVCM D3:VCOM DAC ATT D2:DAC AOUT1 ADC ALC1 VCOM HVCM VCOM: AVDD HVCM: HVDD DAC ATT AVDD HVDD ...
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... VOL2-1 VOL2-0 VOL1-1 VOL1-0 Default DEM1-0: Select De-emphasis Frequency The AK4564 includes the digital de-emphasis filter (tc = 50/ IIR filter. The filter corresponds to three sampling frequencies (32kHz, 44.1kHz and 48kHz). The de-emphasis filter selected by DEM0 and DEM1 registers are enabled for input audio data. ...
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... Table 10. Select cut-off frequency of HPF2 nd order and IIR filter. The cut-off frequency is MIX1 MIX0 Main : Sub 1. 0 0.75 Table 11. Select Mixing value - 37 - [AK4564 HPF2-0 HPF1-1 HFP1-0 FSF fs=48kHz Default OFF 6kHz 7.5kHz 9kHz st order and IIR filter ...
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... Table 12. Select cut-off frequency of LPF1 Cut-off Frequency LPF2-1 LPF2-0 fs=32kHz 0 0 3kHz 0 1 4.5kHz 1 0 6.75kHz 1 1 10.125kHz Table 13. Select cut-off frequency of LPF2 - 38 - [AK4564 LPF2-1 LPF2-0 LPF1-1 LPF1 order and IIR filter. fs=48kHz Default OFF 6kHz 9kHz 13 ...
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... FDTM0 FADEIN/OUT Period 0 0 20ms 0 1 40ms 1 0 48ms 1 1 56ms Table 16. FADEIN/OUT Period TM0 Zero Crossing Timeout Period 0 0 8ms 0 1 16ms 1 0 32ms 1 1 64ms - 39 - [AK4564 ZTM1 ZTM0 WTM1 WTM0 Default Default Default Default 2002/07 ...
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... Table 19. ALC1 Recovery GAIN Step FDATT1 FDATT0 ATT STEP Table 20. FADEIN/OUT ATT Step Setting - 40 - [AK4564 RGAIN1 RGAIN0 LMAT1 LMAT0 ALC1 Output FS + 12dB 1 1 Default Default Default ...
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ALC Mode Control 2 Addr Register Name 08H ALC Mode Control 2 Default LMTH1-0: ALC1 Limiter Detection Level / Recovery Counter Reset Level LMTH1 LMTH0 ALC1 Limier Detection Level ALC1 Recovery Waiting Counter Reset Level 0 0 ALC1 Output -2.5dBFS ...
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ALC Mode Control 3 Addr Register Name 09H ALC Mode Control 3 Default REF7-0: Reference value at ALC1 Recovery Operation. 0.375dB step, 242 Levels During the ALC1 recovery operation, if the REF value exceeds the setting reference value by Gain ...
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... F1H +36.0 +6.0 F0H +35.625 +5.625 EFH +35.25 +5.25 E2H +30.375 +0.375 E1H +30.0 0 E0H +29.625 -0.375 DFH +29.25 -0.75 04H -52.875 -82.875 03H -53.25 -83.25 02H -53.625 -83.625 01H -54 -84 00H MUTE MUTE - 43 - [AK4564 IVOL3 IVOL2 IVOL1 IVOL0 Default 2002/07 ...
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Operation Mode Addr Register Name 0BH Operation Mode Default ALC1: ALC1 Enable Flag 0: Disable (Default) 1: Enable FDOUT: FADEOUT Enable Flag 0: Disable (Default) 1: Enable FDIN: FADEIN Enable Flag 0: Disable (Default) 1: Enable ALC2: ALC2 Enable Flag ...
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... OATT6 OATT5 OATT4 DATA(HEX) ATT Level 58H 0dB 57H -0.75dB 56H -1.5dB 3DH -20.25dB 3CH -21.0dB 3BH -21.75dB 03H -63.75dB 02H -64.5dB 01H -65.25dB 00H MUTE - 45 - [AK4564 OATT3 OATT2 OATT1 OATT0 Default 2002/07 ...
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... C1 + SP0 BEEP1 MUTE SP1 MOUT PDN VCOM SVDD AVDD AK4564 SVSS AVSS BCLK HVCM MCLK MUTET LRCK HVDD CDTI HPR CSN BEEP2 Figure 28. System Connection Diagram - 46 - [AK4564] 10k 36 MIN 2.2 C1 +2.6 3. Analog Supply 2 +2.6 5. 4.7 28 Analog Supply + ...
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... ASAHI KASEI 48pin LQFP(Unit:mm) 9.0 7 0.5 0.22 0.10 n Package & Lead frame material Package molding compound: Epoxy Lead frame material: Lead frame surface treatment: Solder plate (Pb free) MS0140-E-01 PACKAGE 0 0.08 0. 0.5 0 [AK4564] 1.70Max 0.13 0.13 1.40 0.05 0.16 0.07 2002/07 ...
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... AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0140-E-01 MARKING AK4564VQ XXXXXXX XXXXXXXX: Date code identifier IMPORTANT NOTICE - 48 - [AK4564] 2002/07 ...