ak4562 AKM Semiconductor, Inc., ak4562 Datasheet
ak4562
Related parts for ak4562
ak4562 Summary of contents
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... CODEC, PGA : 2.2 Digital I/F : 1.8 3.0V (typ. 2.5V) 11. Power Supply Current IPGA + ADC : 7mA DAC + OPGA : 5.5mA 12 - 13. Package : 28pin QFN Size : 5.2mm x 5.2mm Height : 1mm (max) Pitch : 0.5mm MS0031-E-00 Low Power 20bit FEATURES 2 S 3.0V (typ. 2.5V [AK4562] AK4562 CODEC with PGA 2 S 2000/05 ...
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LIN1 LIN2 RIN1 RIN2 OPGAL LOUT2 OPGAR ROUT2 ROUT1 LOUT1 ADC HPF DAC Control Register I/F Clock Divider CSN CCLK CDTI SSB MCLK (SCK) (SSI) VREF VA AGND VT VD DGND LRCK Audio I/F BCLK Controller SDTO SDTI PDN TST ...
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... ASAHI KASEI n Ordering Guide AK4562VN AKD4562 n Pin Layout OPGAR LOUT2 ROUT2 LIN1 RIN1 LIN2 RIN2 MS0031-E-00 -20 +70 C 28pin QFN (0.5mm pitch) Evaluation Board for AK4562 Top View [AK4562] CDTI LRCK MCLK TST BCLK SDTI ...
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... SSB I Control I/F Mode Select Pin, “L”: AKM Mode, “H”: SSB Mode 26 LOUT1 O Lch DAC Output Pin 27 OPGAL I Lch OPGA Input Pin 28 ROUT1 O Rch DAC Output Pin Note : All digital input pins should not be left floating. MS0031-E-00 PIN/FUNCTION - 4 - [AK4562] 2000/05 ...
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... WARNING: AKM assumes no responsibility for the usage beyond the conditions in this data sheet. MS0031-E-00 ABSOLUTE MAXIMUM RATINGS Symbol min VA -0.3 VD -0.3 VT -0.3 VDA - GND - IIN - VINA -0.3 VIND -0.3 Ta -20 Tstg -65 Symbol min VA 2.2 VD 2.2 / VA-0.3 VT 1.8 VREF - - 5 - [AK4562] max Units 4.6 V 4.6 V 4.6 V 0 VA+0.3 V VT+0 150 C typ max Units 2.5 3 ...
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... Units 20 bits 1.5 1.65 Vpp 9 15 100 dB 0.2 0 ...
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... PM1=1, PM2=0, PM3=0) DA (PM0=0, PM1=0, PM2=1, PM3=1) Power Down (PDN=“L”) Note : 11. In case of power-down mode, all digital input pins including clocks pins (MCLK, BCLK and LRCK) are held VT or DGND. PDN pin is held DGND. MS0031-E-00 (Note 11 [AK4562] 12.0 17 5.5 - ...
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... 22. 0.5 DC CHARACTERISTICS 3.0V) Symbol min VIH 75 VT VIL - VOH VT-0.4 VOL - Iin - - 8 - [AK4562] max Units 17.4 kHz kHz kHz kHz dB 0 20.0 kHz kHz kHz dB 0. Typ max Units - - 0 ...
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... Units 11.2896 12.8 MHz ns ns 16.9344 19.2 MHz ns ns 44.1 50 kHz tBLKL- ...
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... MS0031-E-00 1/fCLK tCLKH tCLKL 1/fs tBLK tBLKH tBLKL Figure 1. Clock Timing tBLR tDLR D20 (MSB) tSDH tCCKL tCCKH tCDS tCDH op0 op1 - 10 - [AK4562] VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL tDSS 50%VT VIH VIL VIH VIL VIH VIL VIH op2 ...
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... Figure 4. WRITE Data Input Timing (AKM) SCK SSI Figure 5. WRITE Data Input Timing (SSB) PDN SDTO MS0031-E- tSCKL tSCKH tSIS tSIH tPW tPWV Figure 6. Reset Timing - 11 - [AK4562] tCSW VIH VIL tCSH VIH VIL VIH D7 VIL VIH VIL VIH VIL VIL 50%VT ...
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... All external clocks (MCLK, BCLK and LRCK) should always be present whenever ADC and DAC are in operation. If these clocks are not provided, the AK4562 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed internally. If the external clocks are not present, the AK4562 should be in the power-down mode ...
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... Digital High Pass Filter The AK4562 has a Digital High Pass Filter (HPF) to cancel DC-offset in ADC and IPGA. The cut-off frequency of the HPF is 3.4Hz at fs=44.1kHz. It also scales with the sampling frequency (fs). n System Reset & Offset Calibration The AK4562 should be reset once by bringing PDN pin “L” after power-up. The control register values are initialized by PDN “ ...
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... PDN signal. Please mute the analog output external if the click noise influences system application. (6). When the external clocks (MCLK, BCLK and LRCK) are stopped, the AK4562 should be in the power down (PDN pin = “L” or PM2-1 bit = “0”) mode. ...
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... Data/Command bit (0: Data, 1: Command) Address or Control Data “1” “1” “1” D0-D3: Device Code, D4-D7: Instruction Code “1” “1” “0” D0-D7: Address or Control Data Figure 13. Control Data Timing (SSB [AK4562 2000/05 ...
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... PM2:Power control of DAC PM3:Power control of OPGA PM3-0 can be partly powered-down by ON/OFF of PM3-0. When PDN pin goes “L”, all circuit in the AK4562 can be powered-down in no relation to PM3-0. When PM3-0 goes all “0”, all circuit in the AK4562 can be also powered-down. However, the contents of control registers are held. ...
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... IMIX ADC IPGA PM0 PM1 IMIX ADC IPGA PM0 PM1 IMIX ADC IPGA PM0 PM1 IMIX ADC IPGA PM0 PM1 Figure 14. Power Management - 17 - [AK4562] DAC OPGA PM3 PM2 DAC OPGA PM3 PM2 DAC OPGA PM3 PM2 DAC OPGA PM3 PM2 2000/05 ...
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... D5 D4 MONO0 ZTM1 ZTM0 SDTI(DAC) 20bit LSB justified 16bit LSB justified 24bit LSB justified Compatible Table 2. Audio Data Format - 18 - [AK4562 DEM1 DEM0 DIF1 DIF0 LRCK BCLK Lch: “H”, Rch: “L” Reset 40fs Lch: “ ...
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... MS0031-E- ZEIP IPGA6 IPGA5 IPGA4 0 GAIN (dB) Step +28.0 +27.5 +27.0 +0.0 0.5dB -0.5 -7.5 -8.0 -9.0 -10.0 1dB -15.0 -16.0 -18.0 -20.0 2dB -38.0 -40.0 -44.0 -48.0 4dB -52.0 MUTE Table 3. Input Gain Setting - 19 - [AK4562 IPGA3 IPGA2 IPGA1 IPGA0 00H (MUTE) Level 2000/05 ...
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... IPGA (OPGA) is newly written 32H, zero crossing operation starts toward IPGA (OPGA) = 32H in state Lch = 31H, Rch = 30H. Internal IPGA (OPGA) value in the AK4562 has the registers of L/R channels independently, according to change IPGA (OPGA) value independently, IPGA (OPGA) value of L/R channels may become a difference in level ...
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... MS0031-E- OPGA6 OPGA5 OPGA4 0 00H (MUTE) HEX CODE OPGA (dB) Step 39H +0 38H -1 37H -2 1dB 18H -33 17H -34 16H -36 15H -38 2dB 03H -74 02H -76 01H -78 00H MUTE Table 4. Output Gain Setting - 21 - [AK4562 OPGA3 OPGA2 OPGA1 OPGA0 Level 2000/05 ...
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... Lch Input only Monaural Recording Rch Input only (3) De-emphasis Include digital de-emphasis filter circuit with tc=50/15us. MS0031-E-00 SW1 + x 0.5 SW2 Figure 16. Monaural Mixing SW1 SW2 MONO1 Lch Rch 0 (L+R)/2 (L+R)/2 0 Lch Lch 1 Rch Rch 1 Table 5. Monaural Mode Setting - 22 - [AK4562] Lch Rch MONO0 2000/05 ...
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... Summary 2-wire Bit Rate: Max. 4Mbps AK4562 has the device code (Max. 4bits, AK4562 is fixed to “05H”.), enable to connect bus to the maximum 16 devices. Each device accepts data after recognizing own device code. Data transmitting to continuity address is enabled by the appointed address at once as there is the auto- increment/auto-decrement functions ...
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... Instruction Code Device code D0-3 bits are the device code, the bus can be connected to maximum 16 devices, however, and the device code is fixed to 05H in the AK4562. Instruction code The following instruction is set by D4-D7 bits. Instruction Code D4 D5 ...
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... ADRSL in 00H 04H is capable to use, but writing should not be done at setting the address except that. MS0031-E-00 : Command WRITE/Auto address INC : Command WRITE/Write address : Data WRITE : Data WRITE (ADRSL) : Data WRITE (ADRSL+1) : Data WRITE (ADRSL+ [AK4562] 2000/05 ...
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... TST pin always fixes to “L”. - AGND and DGND pins connect to AGND. MS0031-E-00 SYSTEM DESIGN CDTI 21 LRCK 20 MCLK 19 TST 18 BCLK 17 SDTI 16 SDTO 0.1u 0.1u 0.1u + 10u + + 10u 10u 1.8V ~ 3.0V Digital Supply 10 ohm - 26 - [AK4562] Micro Controller Audio Controller System AGND Digital GND 2000/05 ...
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... VREF Vpp (typ) centered in the internal common voltage (typ. 0.45 x VA). Usually, the input signal cuts DC with a capacitor. The cut-off frequency is fc=(1/2 RC). The AK4562 can accept input voltages from AGND to VA. The ADC output data format is 2’s complement. The output code is 7FFFFH(@20bit) for input above a positive full scale and 80000H(@20bit) for input below a negative fill scale ...
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... Note : The black parts of back package should be open. n Package & Lead frame material Package molding compound: Lead frame material: Lead frame surface treatment: MS0031-E-00 PACKAGE 0.60 ± 0. 0.05 M 0.50 0.05 Epoxy Cu Solder plate - 28 - [AK4562 2000/05 ...
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... AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0031-E-00 MARKING 4562 XXXX 1 XXXX : Date code identifier IMPORTANT NOTICE - 29 - [AK4562] 2000/05 ...