ak4112b AKM Semiconductor, Inc., ak4112b Datasheet
ak4112b
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ak4112b Summary of contents
Page 1
... ASAHI KASEI The AK4112B is a digital audio receiver (DIR) compatible with 96kHz, 24bits. The channel status decoding supports both consumer and professional modes. The AK4112B can automatically detect a Non-PCM bit stream. When combined with an AK4527B multi channel codec, the two chips provide a system solution for AC-3 applications. The dedicated pins or a serial µ ...
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... ERF Serial Control Mode R MCKO1 MCKO2 Clock Clock Recovery Generator DAIF DEM Decoder AC-3/MPEG Error Detect Detect AUTO ERF Parallel Control Mode - 2 - [AK4112B] XTI XTO X'tal Oscillator 96kHz FS96 Detect DAUX LRCK BICK Audio SDTO I/F TVDD CSN CCLK µp I/F CDTO CDTI P/S=" ...
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... PDN AVDD 9 10 AVSS 11 RX1 RX2/DIF0 12 13 RX3/DIF1 RX4/DIF2 14 MS0078-E-02 -40 ~ +85 °C 28pin VSOP (0.65mm pitch Top View [AK4112B] CM0/CDTO CM1/CDTI OCKS1/CCLK OCKS0/CSN MCKO1 MCKO2 DAUX BICK SDTO LRCK ERF FS96 P/SN AUTO 2004/04 ...
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... Validity Flag Output Pin in Parallel Mode Transmit channel (through data) Output Pin in Serial Mode X'tal Input Pin X'tal Output Pin Power-Down Mode Pin When “L”, the AK4112B is powered-down and reset. External Resistor Pin 18kΩ +/-1% resistor to AVSS externally. Analog Power Supply Pin Analog Ground Pin Receiver Channel 1 This channel is selected in Parallel Mode or default of Serial Mode ...
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... DVDD Symbol min Zin VTH 350 VHY - CHARACTERISTICS Symbol min VIH 70%DVDD VIH 70%DVDD VIL DVSS-0.3 VOH DVDD-0.4 VOL - Iin - =20pF, fs=96kHz, X'tal=12.288MHz [AK4112B] max Units 4.6 V 4.6 V 6.0 V 0.3 V ±10 mA TVDD+0.3 V DVDD+0.3 V °C 85 °C 150 typ max Units 3.3 3.6 V 3.3 AVDD V 3 ...
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... Units 24.576 MHz 24.576 MHz 27.648 MHz 27.648 MHz 108 kHz 48 108 kHz ...
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... Serial Interface Timing (Slave Mode) tDXS tDXH Serial Interface Timing (Master Mode) tCSS tCCKL tCCKH tCDH tCDS C0 C0 R/W Hi-Z WRITE/READ Command Input Timing - 7 - [AK4112B] 50%DVDD tBCKH 50%DVDD 50%DVDD 50%DVDD 50%DVDD 50%DVDD tBSD 50%DVDD 50%DVDD 50%DVDD 50%DVDD 50%DVDD A4 2004/04 ...
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... Hi-Z WRITE Data Input Timing A0 tDCD Hi READ Data Output Timing READ Data Input Timing 2 tPW Power Down & Reset Timing - 8 - [AK4112B] tCSW 50%DVDD 50%DVDD 50%DVDD 50%DVDD 50%DVDD 50%DVDD 50%DVDD D5 tCSW 50%DVDD tCSH 50%DVDD 50%DVDD tCCZ 50%DVDD 30%DVDD 2004/04 ...
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... FS96 pin outputs the value which is set by XFS96. PLL loses lock when the received sync interval is incorrect. Master Clock The AK4112B has two clock outputs, MCKO1 and MCKO2. These clocks are derived from either the recovered clock or from the X'tal oscillator. The frequencies of the master clock outputs (MCKO1 & MCKO2) are set by OCKS0 and OCKS1 as shown in Table 1 ...
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... ASAHI KASEI Clock Source The following circuits are available to feed the clock to XTI pin (#5 pin) of AK4112B. 1) X’tal Note: External capacitance depends on the crystal oscillator (Typ. 10-40pF) 2) External clock External Clock 3) Fixed to the Clock Operation Mode 0 MS0078-E-02 XTI AK4112B XTO XTI ...
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... ASAHI KASEI Sampling Frequency and Pre-emphasis Detect The AK4112B outputs the encoded information of sampling frequency and pre-emphasis in channel status to FS0, FS1 and PEM bits in control register. These information are output from channel 1 at default. It can be switched to channel 2 by CS12 bit in control register. ...
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... The AK4112B goes this mode at default. Therefore, in Parallel Mode, the AK4112B is always placed in this mode and the de-emphasis filter is controlled by the status bits in channel 1. In Serial Mode, DEM0/1 and DFS bits can control the de-emphasis filter when DEAU is “0”. ...
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... ASAHI KASEI System Reset and Power-Down The AK4112B has a power-down mode for all circuits by PDN pin can be partially powerd-down by PWN bit. The RSTN bit initializes the register and resets the internal timing. In Parallel Mode, only the control by PDN pin is enabled. The AK4112B should be reset once by bringing PDN pin = “L” upon power-up. ...
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... For example, by inserting the shield pattern among them. In Parallel Mode, only one channel input (RX1) is available and RX2-4 change to other pins for audio format control. Those pins must be fixed to “H” or “L”. The AK4112B includes the TX output buffer. The output level meets combination 0.5V+/-20% using the external resistor network. The T1 in Figure transformer of 1:1. ...
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... Output Output Output Output - 15 - [AK4112B] V “L” Output Output Output Pin SDTO V TX “L” “L” Output Previous Data Output Output Previous Data Output Output Previous Data Output Output Output ...
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... ERF pin timing at UNLOCK, PAR, BIP, FRERR error MS0078-E-02 (status change ) (state B) Hold “1” Reset READ 03H ERF pin timing at Status Change (error) Hold ”1” (fs: around 20kHz) Free Run Previous Data - 16 - [AK4112B] ERF Hold Time ERF Hold Time Reset READ 04H 2004/04 ...
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... Initialize Read 03H STC is reset, ERF pin ="L" Read 04H ERF pin ="H" YES Mute = "H" Read 03H STC is reset, ERF pin ="L" Read 04H ERF pin ="H" NO YES Figure 4. Error handling sequence Example - 17 - [AK4112B] 2004/04 ...
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... In the format equal or less than 20bit (Mode0-2), LSBs in sub-frame are truncated. In Mode 3-7, the last 4LSBs are auxiliary data (see Figure 5). When the Parity Error, Biphase Error or Frame Length Error occurs in a sub-frame, AK4112B continues to output the last normal sub-frame data from SDTO repeatedly until the error is removed. When the Unlock Error occurs, AK4112B output “ ...
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... Figure 6. Mode 3 Timing Lch Data Figure 7. Mode 4, 6 Timing Lch Data Figure 8. Mode 5, 7 Timing - 19 - [AK4112B Rch Data Rch Data ...
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... CSN. For read operations, the CDTO output goes high impedance after a low-to-high transition of CSN. The maximum speed of CCLK is 5MHz. PDN= “L” resets the registers to their default values. When the state of P/S pin is changed, the AK4112B should be reset by PDN= “L”. CSN ...
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... CB29 CB28 PC7 PC6 PC5 PC4 PC15 PC14 PC13 PC12 PD7 PD6 PD5 PD4 PD15 PD14 PD13 PD12 [AK4112B OCKS1 OCKS0 PWN RSTN IPS1 IPS0 OPS1 OPS0 DEAU DEM1 DEM0 DFS PEM FS1 FS0 RFS96 V FRERR BIP ...
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... C(R191) LRCK SDTO L191 SDTO R190 2 (except I S) MS0078-E- BCU CM1 CM0 RD R/W R/W R C(L0) C(R0) C(L1) 1/4fs R0 R191 L0 L0 L191 R191 - 22 - [AK4112B OCKS1 OCKS0 PWN RSTN R/W R/W R/W R C(L31) C(R31) C(L32) R31 R30 L31 L31 L30 R30 2004/04 ...
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... Disable 1: Enable DIF2-0: Audio Data Format Control MS0078-E- MPAR MSTC CS12 TXE R/W R/W R/W R V/TX DIF2 DIF1 DIF0 DEAU R/W R/W R/W R [AK4112B IPS1 IPS0 OPS1 OPS0 R/W R/W R/W R DEM1 DEM0 DFS R/W R/W R/W R 2004/04 ...
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... This signal goes “H” at the start of frame 0 and maintains “H” until the end of frame 31. MS0078-E- ERF 0 AUTO AUDION STC CRC UNLOCK [AK4112B PEM FS1 FS0 RFS96 FRERR BIP PAR 2004/04 ...
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... PD5 PD4 PD15 PD14 PD13 PD12 PD11 RD Not initialized [AK4112B CA3 CA2 CA1 CA0 CA10 CA9 CA8 CA18 CA17 CA16 CA26 CA25 CA24 CB3 CB2 CB1 CB0 CB10 CB9 CB8 CB18 ...
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... Burst info see Table 15. Length code numbers of bits Table 14. Burst preamble words Table 15. Fields of burst info [AK4112B MSB stuffing repetition time of burst in IEC958 frames ≤ 4096 1536 384 1152 1152 ...
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... Pc Register Register Pd 0 MS0078-E- Repetition time >4096 frames <20mS (Lock time) Stop 2~3 Syncs (B [AK4112B ERF hold time <Repetition time 2004/04 ...
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... DVDD CDTO 28 DVSS 2 CDTI 27 3 TVDD CCLK 26 4 CSN 25 V/TX 5 XTI MCKO1 24 AK4112B XTO 6 MCKO2 23 PDN 7 DAUX BICK 21 9 AVDD SDTO 20 10 AVSS LRCK 19 11 RX1 ERF 18 12 RX2 FS96 RX3 P/SN 14 RX4 15 AUTO - 28 - [AK4112B] Micro- controller DSP and AD/DA 2004/04 ...
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... Seating Plane NOTE: Dimension "*" does not include mold flash. Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: Solder plate MS0078-E-02 PACKAGE 15 14 0.65 Detail A 0.10 Epoxy [AK4112B] 1.25±0.2 A +0.1 0.15-0.05 0.1±0.1 0-10° 2004/04 ...
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... AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0078-E-02 MARKING AKM AK4112BVF XXXBYYYYC Date code identifier Lot number (X : Digit number Alpha character ) Assembly date (Y : Digit number C : Alpha character) IMPORTANT NOTICE - 30 - [AK4112B] Before considering As 2004/04 ...