ak4112a AKM Semiconductor, Inc., ak4112a Datasheet - Page 10

• Manufacturer Part Number: ak4112a
• Description: High Feature 96khz 24bit Dir
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
n n n n Non-PCM (AC-3, MPEG, etc.) Stream Detect
The AK4112A has a Non-PCM steam auto detect function. When the 32bit mode Non-PCM preamble based on Dolby
“AC-3 Data Stream in IEC958 Interface” is detected, the AUTO goes “H”. The 96bit sync code consists of 0x0000,
0x0000, 0x0000, 0x0000, 0xF872 and 0x4E1F. Detection of this pattern will set the AUTO “H”. Once the AUTO is set
“H”, it will remain “H” until 4096 frames pass through the chip without additional sync pattern being detected. When
those preambles are detected, the burst preambles Pc and Pd that follow those sync codes are stored to registers 0DH-
10H.
n n n n Clock Recovery and 96kHz Detect
On chip low jitter PLL has a wide lock range with 22kHz to 108kHz and the lock time is less than 20ms. The 96kHz
detect output pin FS96 goes “H” when the sampling rate is 88.2kHz or more and “L” at 54kHz or less. In X’tal Mode, the
FS96 pin outputs the value which is set by XFS96. PLL loses lock when the received sync interval is incorrect.
n n n n Master Clock
The AK4112A has two clock outputs, MCKO1 and MCKO2. These clocks are derived from either the recovered clock or
from the X'tal oscillator. The frequencies of the master clock outputs (MCKO1 & MCKO2) are set by OCKS0 and
OCKS1 as shown in Table 1. 96kHz sampling is not supported at No.2.
n n n n Clock Operation Mode
The CM0 and CM1 select the clock source of MCKO1/2 and the data source of SDTO via the dedicated pins or the
control register. In Mode 2, the clock source is switched from PLL to X'tal when PLL goes unlock state. In Mode3, the
clock source is fixed to X'tal, but PLL is also operating and the recovered data such as C bits can be monitored.
MS0020-E-00
Mode
0
1
2
3
CM1
0
0
1
1
No.
0
1
2
3
OCKS1
CM0
0
1
0
1
0
0
1
1
ON: Oscillation (Power-up), OFF: STOP (Power-down)
UNLOCK
OCKS0
0
1
-
-
-
0
1
0
1
Table 1. Master clock frequencies select
Table 2. Clock Operation Mode select
OPERATION OVERVIEW
MCKO1
OFF
256fs
256fs
512fs
PLL
ON
ON
ON
ON
- 10 -
X'tal
OFF
ON
ON
ON
ON
MCKO2
256fs
128fs
256fs
Clock source
Test Mode
X'tal
X'tal
X'tal
PLL
PLL
256fs
256fs
512fs
X’tal
32, 44.1, 48, 96
32, 44.1, 48, 96
32, 44.1, 48
FS96
RFS96
XFS96
RFS96
XFS96
XFS96
fs (kHz)
SDTO
RX
DAUX
RX
DAUX
DAUX
Defalt
[AK4112A]
Default
2000/3