ak4116 AKM Semiconductor, Inc., ak4116 Datasheet
ak4116
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ak4116 Summary of contents
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... ASAHI KASEI The AK4116 is a low power S/PDIF AES/EBU receiver supporting resolution up to 24-bit. The integrated channel status decoder supports both consumer and professional modes. The AK4116 can automatically detect a Non-PCM bit stream. Combining the AK4116 with a multi-channel codec such as AKM’s AK4527B or AK4529 can create a complete AC-3 system ...
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... Block Diagram AVSS RX0 DVDD DVSS AC-3/MPEG Detect MS0156-E-03 AVDD R XTI X'tal Clock Oscillator Recovery DAIF Decoder Error & Q-subcode STATUS buffer Detect INT0 INT1 - 2 - [AK4116] XTO Clock MCKO Generator LRCK Audio BICK I/F SDTO DAUX PDN CSN CCLK µP I/F CDTI CDTO 2005/08 ...
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... ASAHI KASEI Ordering Guide -40 ~ +85 °C AK4116VN Pin Layout RX0 DVDD DVSS XTI XTO MS0156-E-03 20pin QFN (0.5mm pitch Top View [AK4116] INT1 CSN CCLK CDTI CDTO 2005/08 ...
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... Chip Select Pin Interrupt 1 Pin Interrupt 0 Pin Power-Down & Reset Pin When “L”, the AK4116 is powered-down and reset, and all output pins go to “L” and the control registers are reset to default state. Analog Ground Pin External Resistor Pin resistor to AVSS externally. ...
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... AVDD 2.7 DVDD 2.7 Symbol min Zin - VTH 350 CHARACTERISTICS Symbol min VIH 70%DVDD VIL DVSS-0.3 VOH DVDD-0.4 VOL - Iin - =20pF. AVDD=5mA (typ), DVDD=9mA (typ [AK4116] max Units 4.6 V 4.6 V 0.3 V ±10 mA DVDD+0.3 V AVDD+0.3 V °C 85 °C 150 typ max Units 3.3 3.6 V 3.3 AVDD V typ ...
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... Units 24.576 MHz 24.576 MHz 24.576 MHz KHz 48 kHz 48 kHz 48 kHz 55 % 64fs ...
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... Figure 1. Clock Timing tDXS tDXH Figure 2. Serial Interface Timing - 7 - [AK4116] VIH VIL = tECLKL x fECLK x 100 50%DVDD = tMCKL x fMCK x 100 VIH VIL = tLRL 100 50%DVDD 50%DVDD tBSD 50%DVDD ...
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... C1 C0 R/W Hi-Z tCSH Hi-Z Figure 4. WRITE Data Input Timing A0 tDCD Hi Figure 5. READ Data Output Timing [AK4116] VIH VIL VIH VIL VIH A4 VIL tCSW VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL 50%DVDD ...
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... ASAHI KASEI CSN CCLK CDTI CDTO D3 PDN MS0156-E- Figure 6. READ Data Input Timing 2 tPW Figure 7. Power Down & Reset Timing - 9 - [AK4116] tCSW VIH VIL tCSH VIH VIL VIH VIL tCCZ 50%DVDD VIL 2005/08 ...
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... DTS-CD bitstearm, while it does not detect 16bit sync word (0x7FFE8001). Clock Recovery The on-chip, low jitter PLL has a wide lock range of 32kHz to 48kHz and a lock time of less than 20ms. The AK4116 has a sampling frequency detect function (32kHz, 44.1kHz and 48kHz) that uses either clock comparison against the X’tal oscillator or the channel status information ...
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... ASAHI KASEI Master Clock Output The AK4116 has a master clock output pin, MCKO. In PLL mode, PLL lock range 48kHz and the MCKO frequency is fixed to 256fs. In the X’tal mode, XCKS1-0 bits select the ratio of the X’tal frequency to fs (sampling frequency). The DIV bit selects the ratio (x1 or x1/2) of the MCKO frequency to the X’ ...
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... ASAHI KASEI Clock Source The following circuits are available to feed a clock into the XTI pin of AK4116. 1) X’tal mode The X’tal with proper value should be connected between XTI and XTO pins. Note: External capacitance depends on the crystal oscillator (Typ.10-40pF). 2) External clock mode EXCK bit should be set to “ ...
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... ASAHI KASEI Sampling Frequency and Pre-emphasis Detection The AK4116 has two methods for detecting the sample frequency: 1) Clock comparison between recovered clock and the X’tal oscillator FS3-0 bits indicate the detected RX input frequency referred to X’tal frequency. XTL1-0 bits select the reference X’ ...
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... ASAHI KASEI System Reset and Power-Down The AK4116 has a full power-down mode for all circuits that is activated by the PDN pin, and a partial power-down mode activated by the PWN bit. The RSTN bit initializes the internal registers and timing. The AK4116 should be reset once at power-up by bringing PDN pin = “ ...
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... Note: When using a coaxial input, if the coupling level to this input from the next RX input line pattern exceeds 50mV, incorrect operation may occur. This can be reduced or prevented by adding a decoupling capacitor. 3.3V Optical Fiber Optical Receiver Figure 12. Consumer Input Circuit (Optical Input; Using 3.3V Optical Receiver) MS0156-E-03 0.1uF 75Ω 470 O [AK4116] RX AK4116 3.3V RX AK4116 2005/08 ...
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... ASAHI KASEI Q-subcode buffers The AK4116 has a Q-subcode buffer for CD application. The AK4116 takes Q-subcode into registers under the following conditions: 1) The sync word (S0,S1) is consists of least 16 “0”s. 2) The start bit is “1”. 3) Those 7bits Q-W follows to the start bit. 4) The distance between two start bits is 8-16 bits. ...
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... CINT bit goes to “1”, it stays “1” until the register is read. INT pin holds “H” for one sub-frame, then goes to “L” in this case. When the AK4116 loses lock, the channel status bits are initialized. In this initial state, INT0 outputs the OR’ed signal between UNLCK and PAR bits. INT1 outputs the OR’ed signal to AUTO, V and AUDION. INT1-0 pins are “L” when the PLL is OFF (Clock Operation Mode 1) ...
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... Command MCKO,BICK,LRCK (UNLCK) MCKO,BICK,LRCK (except UNLCK) SDTO (UNLCK) SDTO (PAR error) SDTO (others) MS0156-E-03 (Interrupt) Hold ”1” Free Run (fs: around 20kHz) Previous Data Figure 16. INT1-0 pin timing - 18 - [AK4116] Hold Time (max: 4096/fs) Hold Time = 0 Reset READ 05H Normal Operation 2005/08 ...
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... Release Muting Figure 17. Interrupt Handling Sequence Example 1 MS0156-E-03 PDN pin ="L" to "H" Initialize Read 05H INT0/1 pin ="H" No Yes Mute DAC output Read 05H (Each Error Handling) Read 05H (Resets registers) No INT0/1 pin ="H" Yes - 19 - [AK4116] 2005/08 ...
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... MS0156-E-03 PDN pin ="L" to "H" Initialize Read 05H INT1 pin ="H" No Yes Read 05H and Detect QSUB= “1” (Read Q-buffer) No New data QCRC = “0” Yes No INT1 pin ="L" Yes New data is valid - 20 - [AK4116] is invalid 2005/08 ...
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... In Modes 3-7, the last four LSBs are auxiliary data (see Figure 19). When a Parity Error, Biphase Error or Frame Length Error occurs in a sub-frame, the AK4116 continues to output the last normal sub-frame data from SDTO repeatedly until the error is removed. When an Unlock Error occurs, the AK4116 outputs “ ...
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... Figure 21. Mode 3 Timing Lch Data Figure 22. Mode 4 Timing Lch Data Figure 23. Mode 5 Timing - 22 - [AK4116 Rch Data Rch Data ...
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... C0 R Hi C1,C0: Chip Address (Fixed to “00”) R/W: READ/WRITE (0:READ, 1:WRITE) A4-A0: Register Address D7-D0: Control Data Figure 24. 4-wire Serial Control I/F Timing - 23 - [AK4116 Hi 2005/08 ...
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... Q38 Q49 Q48 Q47 Q46 Q57 Q56 Q55 Q54 Q65 Q64 Q63 Q62 Q73 Q72 Q71 Q70 Q81 Q80 Q79 Q78 - 24 - [AK4116 XTL1 XTL0 PWN RSTN XCKS1 XCKS0 CM1 CM0 EFH0 DIF2 DIF1 DIF0 MAUD0 MSTC0 MCIT0 MQIT0 MAUD1 ...
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... Same frequency as X’tal (Default) 1: Half frequency of X’tal MS0156-E- EXCK R DIV R [AK4116 XTL1 XTL0 PWN RSTN R/W R/W R/W R XCKS1 XCKS0 CM1 CM0 R/W R/W R/W R 2005/08 ...
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... Channel 2 This bit selects which channel status is used to derive C-bit buffers, AUDION, PEM, FS3-0, Pc, Pd and CRC. MS0156-E- CS12 EFH1 RD RD R/W R 01: 1024 LRCK (Default) 11: 4096 LRCK - 26 - [AK4116 EFH0 DIF2 DIF1 DIF0 R/W R/W R/W R 2005/08 ...
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... The factor whose mask bit is set to “0” affects INT1 pin operation. MS0156-E- MULK0 MPAR0 MAUT0 MV0 R/W R/W R/W R MULK1 MPAR1 MAUT1 MV1 R/W R/W R/W R [AK4116 MAUD0 MSTC0 MCIT0 MQIT0 R/W R/W R/W R MAUD1 MSTC1 MCIT1 MQIT1 R/W R/W R/W R 2005/08 ...
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... UNLCK: PLL Lock Status 0: Lock QINT, CINT, STC and PAR bits are initialized when 05H is read. MS0156-E- PAR AUTO V AUDION Changed 1: Changed 1: Detect 1: Non Audio 1: Invalid 1: Detect 1:Error 1: Unlock - 28 - [AK4116 STC CINT QINT 2005/08 ...
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... DTSCD NPCM PEM Detect 1: Detect Error 1: Error - 29 - [AK4116 FS3 FS2 FS1 FS0 CCRC QCRC 2005/08 ...
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... Q48 Q47 Q46 Q57 Q56 Q55 Q54 Q65 Q64 Q63 Q62 Q73 Q72 Q71 Q70 Q81 Q80 Q79 Q78 RD Not initialized - 30 - [AK4116 CR3 CR2 CR1 CR0 CR11 CR10 CR9 CR8 CR19 CR18 CR17 CR16 CR27 CR26 CR25 CR24 CR35 ...
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... LSB 16 bits of bitstream 0 Burst_payload repetition time of the burst Figure 25. Data structure in IEC60958 Contents sync word 1 sync word 2 Burst info Length code Table 8. Burst preamble words - 31 - [AK4116 MSB stuffing Value 0xF872 0x4E1F see Table 9 numbers of bits 2005/08 ...
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... MS0156-E-03 repetition time of burst in IEC958 frames ≤4096 1536 384 1152 1152 1024 384 1152 512 1024 2048 512 1024 Table 9. Fields of burst info [AK4116] 2005/08 ...
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... MS0156-E- Repetition time >4096 frames Figure 26. Timing example 1 <20mS (Lock time) Stop 2~3 Syncs (B Figure 27. Timing example [AK4116 INT0 hold time <Repetition time Pc ...
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... X’tal. (Typ.10-40pF) (2) AVSS and DVSS must be connected the same ground plane. MS0156-E-03 SYSTEM DESIGN 12k 10u 0. RX0 INT1 15 DVDD CSN 2 14 AK4116 3 DVSS CCLK 13 XTI CDTI 4 12 XTO CDTO 5 11 AD/DA Figure 28. Typical Connection Diagram - 34 - [AK4116] Micro- controller 2005/08 ...
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... QFN (Unit: mm) 4.20 ± 0.10 4.00 ± 0.05 C0.7 0.22 ± 0.05 0.05 0.60 ± 0.10 Note: The black parts of back package should be open. Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: Solder (Pb free) plate MS0156-E-03 PACKAGE C0.2 B 45.0° 0.50 1. 0.05 S Epoxy [AK4116] 45.0° 2005/08 ...
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... Figure 15. Q-subcode register map Addr = 16H ∼ 1FH 32 Table 9. Fields of burst info Pc Value 7: reserved Value 14: reserved Value 15: reserved Value 27: (Reserved for MPEG-4 AAC data) Value 28: MPEG-2 AAC data 3 Ordering Guide: AK4116VF - 36 - [AK4116] settings can be controlled via “ The DIF2-0 11H ∼ 1AH MPEG2 AAC ADTS ...
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... AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0156-E-03 IMPORTANT NOTICE - 37 - [AK4116] Before considering As 2005/08 ...