ak4114 AKM Semiconductor, Inc., ak4114 Datasheet
ak4114
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ak4114 Summary of contents
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... ASAHI KASEI High Feature 192kHz 24bit Digital Audio Interface Transceiver The AK4114 is a digital audio transceiver supporting 192kHz, 24bits. The channel status decoder supports both consumer and professional modes. The AK4114 can automatically detect a Non-PCM bit stream. When combined with the multi channel codec (AK4527B or AK4529), the two chips provide a system solution for AC-3 applications. The dedicated pins or a serial µ ...
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... AVDD R XTI X'tal Clock Oscillator Recovery DEM DAIF Decoder Error & AC-3/MPEG STATUS Detect Detect B,C,U,VOUT INT0 INT1 Parallel Control Mode - 2 - [AK4114] XTO Clock MCKO1 Generator MCKO2 LRCK Audio BICK I/F SDTO DAUX PDN CSN CCLK Q-subcode µP I/F CDTO buffer CDTI P/S=”L” ...
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... Pin Layout IPS0/RX4 1 AVSS 2 DIF0/RX5 3 TEST2 4 DIF1/RX6 5 AVSS 6 DIF2/RX7 7 IPS1/IIC 8 P/SN 9 XTL0 10 XTL1 11 VIN 12 MS0098-E-04 48pin LQFP (0.5mm pitch AK4114VQ Top View [AK4114] INT0 OCKS0/CSN/CAD0 OCKS1/CCLK/SCL CM1/CDTI/SDA CM0/CDTO/CAD1 PDN XTI XTO DAUX MCKO2 BICK SDTO 2004/03 ...
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... Digital Power Supply Pin, 3.3V Digital Ground Pin Master Clock Output 1 Pin Channel Clock Pin Audio Serial Data Output Pin Audio Serial Data Clock Pin Master Clock Output 2 Pin Auxiliary Audio Data Input Pin X'tal Output Pin X'tal Input Pin - 4 - [AK4114] 2004/03 ...
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... MS0098-E-04 PIN/FUNCTION (Continued) Function Power-Down Mode Pin When “L”, the AK4114 is powered-down and reset. Master Clock Operation Mode 0 Pin in Parallel Mode Control Data Output Pin in Serial Mode, IIC= “L”. Chip Address 1 Pin in Serial Mode, IIC= “H”. Master Clock Operation Mode 1 Pin in Parallel Mode Control Data Input Pin in Serial Mode, IIC= “ ...
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... Zin VTH 200 VHY CHARACTERISTICS Symbol min (Note 4) (Note 5) VIH 70%DVDD VIL DVSS-0.3 VOH DVDD-0.4 VOL - VOL - Iin - =20pF, fs=192kHz, X'tal=24.576MHz, Clock Operation Mode [AK4114] max Units 4.6 V 4.6 V 6.0 V 0.3 V ±10 mA TVDD+0.3 V DVDD+0.3 V °C 70 °C 150 typ max Units 3.3 3 ...
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... Units 24.576 MHz 24.576 MHz 24.576 MHz 24.576 MHz 192 kHz 192 kHz ...
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... Cb - tPW 150 2 C components conveys a license under the Philips 2 C system, provided the system conform to the [AK4114] typ max Units 100 kHz µs - µs - µs - µs - µs - µ 1000 ns 300 µs ...
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... Figure 1. Clock Timing tBCK tBLR tLRB tBCKL tLRM tBSD tDXS tDXH - 9 - [AK4114] VIH VIL = tECLKL x fECLK x 100 50%DVDD = tMCKL1 x fMCK1 x 100 50%DVDD = tMCKL2 x fMCK2 x 100 VIH VIL = tLRL 100 VIH VIL tBCKH VIH ...
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... Figure 3. Serial Interface Timing (Master Mode) CSN CCLK CDTI CDTO Figure 4. WRITE/READ Command Input Timing in 4-wire serial mode MS0098-E-04 tDXS tDXH tCSS tCCK tCCKL tCCKH tCDH tCDS C1 C0 R/W Hi [AK4114] 50%DVDD 50%DVDD tBSD 50%DVDD VIH VIL VIH VIL VIH VIL VIH A4 VIL 2004/03 ...
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... CSN CCLK CDTI CDTO D3 Figure 7. READ Data Input Timing 2 in 4-wire serial mode MS0098-E-04 tCSH Hi-Z A0 tDCD Hi [AK4114] tCSW VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL 50%DVDD D5 tCSW VIH VIL tCSH VIH ...
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... ASAHI KASEI SDA tLOW tR tBUF SCL tHD:STA tHD:DAT Stop Start PDN MS0098-E-04 tHIGH tF tSU:DAT tSU:STA Start 2 Figure Bus mode Timing tPW Figure 9. Power Down & Reset Timing - 12 - [AK4114] VIH VIL tSP VIH VIL tSU:STO Stop VIL 2004/03 ...
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... Clock Recovery On chip low jitter PLL has a wide lock range with 32kHz to 192kHz and the lock time is less than 20ms. The AK4114 has the sampling frequency detect function. By either the clock comparison against X’tal oscillator or using the channel status, AK4114 detects the sampling frequency (32kHz, 44 ...
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... ASAHI KASEI Clock Source The following circuits are available to feed the clock to XTI pin of AK4114. 1) X’tal Note: External capacitance depends on the crystal oscillator (Typ. 10-40pF) 2) External clock External Clock 3) Fixed to the Clock Operation Mode 0 MS0098-E-04 XTI AK4114 XTO Figure 10. X’tal mode ...
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... ASAHI KASEI Sampling Frequency and Pre-emphasis Detection The AK4114 has two methods for detecting the sampling frequency as follows. 1. Clock comparison between recovered clock and X’tal oscillator 2. Sampling frequency information on channel status Those could be selected by XTL1, 0 bits. And the detected frequency is reported on FS3-0 bits. ...
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... Table 8. De-emphasis Manual Control at DEAU = “0” System Reset and Power-Down The AK4114 has a power-down mode for all circuits by PDN pin can be partially powerd-down by PWN bit. The RSTN bit initializes the register and resets the internal timing. In Parallel Mode, only the control by PDN pin is enabled. The AK4114 should be reset once by bringing PDN pin = “ ...
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... Table 9. Recovery Data Select 1/4fs C(L0) C(R0) C(L1) L0 L191 R191 L191 R191 L0 Figure 13 output/input timings - 17 - [AK4114] RX0 Default RX1 RX2 RX3 RX4 RX5 RX6 RX7 C(L31) C(R31) C(L32) L31 L30 R30 L30 R30 L31 2004/03 ...
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... CT39-CT0 bits in control registers. When bit0= “0”(consumer mode), bit20-23(Audio channel) could not be controlled directly but be controlled by CT20 bit. When the CT20 bit is “1”, AK4114 outputs “1000” as C20-23 for left channel and output “0100” at C20-23 for right channel automatically. When CT20 bit is “0”, AK4114 outputs “0000” set as “ ...
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... ASAHI KASEI Double sampling frequency mode When MONO bit = “1”, the AK4114 outputs data with double speed according to “Single channel double sampling frequency mode” of AES3. For example, when 192kHz mono data is transmitted or received, L/R channels of 96kHz biphase data are used. In this case, 1 frame is 96kHz and LRCK frequency is 192kHz. ...
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... ASAHI KASEI 2) TX When MONO bit = “1” and TLR bit = “0”, the AK4114 outputs Lch data through TX1 as biphase signal. When MONO bit = “1” and TLR bit = “1”, then Rch data. LRCK (except IIS) LRCK (IIS) Serial Data ...
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... Reset all the AK4114s by PDN pin = “L” → “H” or RSTN bit = “0” → “1”. (2) Set all the AK4114s to MONO mode while they are still in slave mode. (3) Set one of the AK4114s to master mode so that LRCK is input to all other AK4114s at the same time, or LRCK should be input to all the AK4114s at the same time. ...
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... The AK4114 includes the TX output buffer. The output level meets combination 0.5V+/-20% using the external resistor network. The T1 in Figure transformer of 1: DVSS Note: When the AK4114 is in the power-down mode (PDN= “L”), power supply current can be suppressed by using AC couple capacitor as following figure since TX1 pin output becomes uncertain at power-down mode. 0.1uF TX1 DVSS MS0098-E-04 0 ...
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... ASAHI KASEI Q-subcode buffers The AK4114 has Q-subcode buffer for CD application. The AK4114 takes Q-subcode into registers by following conditions. 1. The sync word (S0,S1) is constructed at least 16 “0”s. 2. The start bit is “1”. 3. Those 7bits Q-W follows to the start bit. 4. The distance between two start bits are 8-16 bits. ...
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... Each INT0/1 pins can mask those eight events individually. Once PAR, QINT and CINT bit goes to “1”, those registers are held to “1” until those registers are read. While the AK4114 loses lock, registers regarding C-bit or U-bits are not initialized and keep previous value ...
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... EFH0-1 bits) after the all events are removed. Once those PAR, QINT or CINT bit goes “1”, it holds “1” until reading those registers. While the AK4114 loses lock, the channel status an Q-subcode bits are not updated and holds the previous data. At initial state, INT0 outputs the ORed signal between UNLOCK and PAR, INT1 outputs the ORed signal among AUTO, DTSCD and AUDION ...
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... UNLOCK) SDTO (UNLOCK) SDTO (PAR error) SDTO (others) Vpin (UNLOCK) Vpin (except UNLOCK) MS0098-E-04 (Error) Hold ”1” Free Run (fs: around 20kHz) Previous Data Figure 26. INT0/1 pin timing - 26 - [AK4114] Hold Time (max: 4096/fs) Hold Time = 0 Reset READ 06H Normal Operation 2004/03 ...
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... ASAHI KASEI Release Muting Figure 27. Error Handling Sequence Example 1 MS0098-E-04 PD pin ="L" to "H" Initialize Read 06H INT0/1 pin ="H" No Yes Mute DAC output Read 06H (Each Error Handling) Read 06H (Resets registers) No INT0/1 pin ="H" Yes - 27 - [AK4114] 2004/03 ...
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... Figure 28. Error Handling Sequence Example (for Q/CINT) MS0098-E-04 PD pin ="L" to "H" Initialize Read 06H INT1 pin ="H" No Yes Read 06H and Detect QSUB= “1” (Read Q-buffer) No New data QCRC = “0” is invalid Yes No INT1 pin ="L" Yes New data is valid - 28 - [AK4114] 2004/03 ...
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... Figure 29). When the Parity Error, Biphase Error or Frame Length Error occurs in a sub-frame, AK4114 continues to output the last normal sub-frame data from SDTO repeatedly until the error is removed. When the Unlock Error occurs, AK4114 output “ ...
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... Lch Data Mode4 : LRCK, BICK : Output Mode6 : LRCK, BICK : Input Lch Data Mode5 : LRCK, BICK : Output Mode7 : LRCK, BICK : Input - 30 - [AK4114 Rch Data ...
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... CSN. For read operations, the CDTO output goes high impedance after a low-to-high transition of CSN. The maximum speed of CCLK is 5MHz. PDN= “L” resets the registers to their default values. When the state of P/S pin is changed, the AK4114 should be reset by PDN= “L”. CSN ...
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... C-bus system (max : 400kHz). (2)-1. Data transfer All commands are preceded by a START condition. After the START condition, a slave address is sent. After the AK4114 recognizes the START condition, the device interfaced to the bus waits for the slave address to be transmitted over the SDA line ...
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... In the read mode, the slave, AK4114 will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge acknowledge is detected and no STOP condition is generated by the master, the slave will continue to transmit data ...
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... The AK4114 is capable of more than one byte write operation by one sequence. After receipt of the third byte, the AK4114 generates an acknowledge, and awaits the next data again. The master can transmit more than one words instead of terminating the write cycle after the first data word is transferred. After the receipt of each data, the internal 5bits address counter is incremented by one, and the next data is taken into next address automatically. If the address exceed 1FH prior to generating the stop condition, the address counter will “ ...
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... Therefore, if the last access (either a read or write) was to address n, the next CURRENT READ operation would access data from the address n+1. After receipt of the slave address with R/W bit set to “1”, the AK4114 generates an acknowledge, transmits 1byte data which address is set by the internal address counter and increments the internal address counter the master does ...
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... Q49 Q48 Q47 Q46 Q57 Q56 Q55 Q54 Q65 Q64 Q63 Q62 Q73 Q72 Q71 Q70 Q81 Q80 Q79 Q78 - 36 - [AK4114 OCKS1 OCKS0 PWN RSTN DEAU DEM1 DEM0 DFS TX0E OPS02 OPS01 OPS00 DIT IPS2 IPS1 IPS0 MPE0 MAUD0 MPAR0 ...
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... MONO: Double sampling frequency mode enable 0: Stereo mode 1: Mono mode MS0098-E- CS12 BCU CM1 CM0 R/W R/W R/W R MONO DIF2 DIF1 DIF0 R/W R/W R/W R [AK4114 OCKS1 OCKS0 PWN RSTN R/W R/W R/W R DEAU DEM1 DEM0 DFS R/W R/W R/W R 2004/03 ...
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... TX0E R/W R/W R/W R EFH1 EFH0 UDIT TLR R/W R/W R/W R channel 1: Recovered U bit is used for DIT (loop mode for U bit) 01: 1024 LRCK 11: 4096 LRCK - 38 - [AK4114 OPS02 OPS01 OPS00 R/W R/W R/W R DIT IPS2 IPS1 IPS0 R/W R/W R/W R ...
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... MQI1: Mask Enable for QINT bit 0: Mask disable 1: Mask enable MS0098-E- MQI0 MAT0 MCI0 MUL0 R/W R/W R/W R MQI1 MAT1 MCI1 MUL1 R/W R/W R/W R [AK4114 MDTS0 MPE0 MAN0 MPR0 R/W R/W R/W R MDTS1 MPE1 MAN1 MPR1 R/W R/W R/W R 2004/03 ...
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... Non Audio Detect 1: Out of Lock 1: Changed 1: Detect 1: Changed FS3 FS2 FS1 FS0 1:Error 1:Error 1:Invalid - 40 - [AK4114 PEM AUDION PAR QCRC CCRC ...
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... D5 D4 PC7 PC6 PC5 PC4 PC15 PC14 PC13 PC12 PC11 PD7 PD6 PD5 PD4 PD15 PD14 PD13 PD12 PD11 RD Not initialized - 41 - [AK4114 CR3 CR2 CR1 CR0 CR10 CR9 CR8 CR18 CR17 CR16 CR26 CR25 CR24 CR34 CR33 CR32 D3 D2 ...
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... Q56 Q55 Q54 Q53 Q65 Q64 Q63 Q62 Q61 Q73 Q72 Q71 Q70 Q69 Q81 Q80 Q79 Q78 Q77 RD Not initialized - 42 - [AK4114 Q12 Q11 Q10 Q20 Q19 Q18 Q28 Q27 Q26 Q36 Q35 Q34 Q44 Q43 Q42 Q52 ...
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... LSB 16 bits of bitstream 0 Burst_payload repetition time of the burst Figure 44. Data structure in IEC60958 Contents sync word 1 sync word 2 Burst info Length code Table 15. Burst preamble words - 43 - [AK4114 MSB stuffing Value 0xF872 0x4E1F See Table 16 Numbers of bits 2004/03 ...
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... MS0098-E-04 Repetition time of burst in IEC60958 frames ≤4096 1536 384 1152 1152 1024 384 1152 512 1024 2048 512 1024 Table 16. Fields of burst info [AK4114] 2004/03 ...
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... MS0098-E- Repetition time >4096 frames Figure 45. Timing example 1 <20mS (Lock time) Stop 2~3 Syncs (B Figure 46. Timing example [AK4114 INT0 hold time <Repetition time Pc ...
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... Digital signals, especially clocks, should be kept away from the R pin in order to avoid an effect to the clock jitter performance. MS0098-E-04 SYSTEM DESIGN Digital Ground + 10µF 0.1µF R INT0 36 CSN 35 CCLK 34 CDTI 33 CDTO 32 AK4114 X’tal=11.2896MHz 31 PDN C XTI 30 C XTO 29 DAUX 28 MCKO2 27 26 BICK SDTO 25 + +3.3V Digital Supply - 46 - [AK4114] Microcontroller CODEC SDTO (AK4626) MCLK BICK LRCK DSP 2004/03 ...
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... ASAHI KASEI 48pin LQFP(Unit:mm) 9.0 ± 0.2 7 0.22 ± 0.08 0.5 0.10 Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: Solder (Pb free) plate MS0098-E-04 PACKAGE 0.10 M 0° ∼ 10° 0.5 ± 0.2 Epoxy [AK4114] 1.70Max 0.13 ± 0.13 1.40 ± 0.05 0.16 ± 0.07 2004/03 ...
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... AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0098-E-04 MARKING AK4114VQ XXXXXXX XXXXXXXX: Date code identifier IMPORTANT NOTICE - 48 - [AK4114] Before considering As 2004/03 ...