ak4115 AKM Semiconductor, Inc., ak4115 Datasheet
ak4115
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ak4115 Summary of contents
Page 1
... ASAHI KASEI High Feature 192kHz 24bit Digital Audio Interface Transceiver The AK4115 is a 24-bit stereo digital audio transceiver that supports sampling rates up to 216kHz. The channel status bit decoder supports both consumer and professional modes and can automatically detect Non-PCM bit streams such as Dolby Digital or MPEG. The AK4115 supports a wide array of features a couple of them being ...
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... RX4 Selector RX5 RX6 RX7 TX0 TXP1 TXN1 DIT TVDD TVSS DVDD DVSS OVDD OVSS XTL1 XTL0 VIN Figure 1. AK4115 Block Diagram in serial mode MS0573-E-00 AVSS AVDD R VCOM FILT Clock Recovery DEM DAIF Decoder ASYNC Error & AC-3/MPEG STATUS Detect Detect ...
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... Selector RX3 IPS0 DIF0 DIF1 TX0 TXP1 DIT TXN1 TVDD TVSS DVDD DVSS OVDD OVSS XTL1 XTL0 VIN Figure 2. AK4115 Block Diagram in parallel mode MS0573-E-00 AVSS AVDD R VCOM FILT XSEL Clock Clock Recovery Selector DEM DAIF Decoder Error & AC-3/MPEG STATUS ...
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... ASAHI KASEI Ordering Guide -20 ~ +85 °C AK4115VQ AK4115 Evaluation board for AK4115 Pin Layout DIF0/RX5 1 TEST 2 DIF1/RX6 3 PDN 4 XSEL/RX7 5 DVDD 6 VIN 7 DAUX 8 DVSS 9 MCKO1 10 11 MCKO2 OVDD 12 OVSS 13 BICK 14 SDTO 15 LRCK 16 MS0573-E-00 64pin LQFP (0.5mm pitch) Top View - 4 - [AK4115] 48 FILT 47 XTL1 ...
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... This pin must be connected to AVSS. Audio Data Interface Format #1 Pin in parallel mode Receiver Channel #6 Pin in serial mode Power-Down Mode Pin When “L”, the AK4115 is powered-down and reset. X’tal Oscillator Selection Pin in parallel mode “L”: X’tal #1 is powered-up. “H”: X’tal #2 is powered-up. ...
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... Receiver Channel #2 Pin Analog Ground Pin Receiver Channel #3 Pin Analog Power Supply Pin, 3.3V Input Channel Select #0 Pin in parallel mode Receiver Channel #4 Pin in serial mode - 6 - [AK4115] (Internal biased pin) (Internal biased pin) (Internal biased pin) (Internal biased pin) (Internal biased pin) (Internal biased pin) ...
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... These pins should be DVSS when BCU_IO bit is “0”. These pins should be open in master mode. These pins should be connected to DVSS in slave mode. Setting These pins should be open. This pin should be connected to AVSS. This pin should be open. These pin should be connected to DVSS. These pins should be open [AK4115] 2006/12 ...
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... IIN - VIN -0.3 Ta -20 Tstg -65 Symbol min AVDD 2.7 DVDD 2.7 OVDD 2.7 TVDD DVDD AVDD – DVDD -0.3 AVDD – OVDD -0.3 OVDD – DVDD -0 [AK4115] max Units 4.6 V 4.6 V 4.6 V 6.0 V 0.3 V 0.3 V 0.3 V 0.3 V ±10 mA “TVDD+0.3” or 6.0 V °C 85 °C 150 typ max Units 3.3 3 ...
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... VIH 70%DVDD VIL DVSS-0.3 VAC 0.5 VOH OVDD-0.4 VOL - VOL - VTXO0 0.4 RTXPN 88 VTXO1 0.4 Iin - =20pF, fs=216kHz, X'tal=24.576MHz, Clock Operation Mode [AK4115] typ max Units 10 - kΩ mVpp - 216 kHz 100 - ps RMS 300 - ps RMS RMS RMS typ max ...
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... Units - 24.576 MHz - 27.648 MHz 27.648 MHz 27.648 MHz 216 kHz - 216 kHz - ...
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... Cb - tSP 0 tPW 150 - 11 - [AK4115] typ max Units - - 400 kHz µ µ µ µ µ ...
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... Figure 3. Clock Timing - 12 - [AK4115] VIH VIL = tECLKL x fECLK x 100 50%OVDD = tMCKL1 x fMCK1 x 100 50%OVDD = tMCKL2 x fMCK2 x 100 VIH VIL = tLRL 100 VIH ...
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... Figure 6. Serial Interface Timing 2 (Slave Mode) MS0573-E-00 tBCK tBLR tLRB tBCKL tBCKH tLRM tBSD tDXS tDXH tDXS tDXH tEBCK tEBLR tELRB tEBCKL tEBCKH tEDXS tEDXH - 13 - [AK4115] VIH VIL VIH VIL 50%OVDD VIH VIL 50%OVDD 50%OVDD tBSD 50%OVDD VIH VIL VIH VIL VIH VIL VIH VIL 2006/12 ...
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... CDTO Figure 9. WRITE Data Input Timing in 4-wire serial mode MS0573-E-00 tEDXS tEDXH tCSS tCCK tCCKL tCCKH tCDH tCDS Hi-Z tCSH Hi [AK4115] 50%OVDD 50%OVDD VIH VIL VIH VIL VIH VIL VIH 0 VIL tCSW VIH VIL VIH VIL VIH VIL 2006/12 ...
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... PDN MS0573-E-00 A0 tDCD Hi tHIGH tF tSU:DAT tSU:STA Start 2 Figure 12 Bus mode Timing tPW Figure 13. Power Down & Reset Timing - 15 - [AK4115] VIH VIL VIH VIL VIH VIL D5 50%OVDD tCSW VIH VIL tCSH VIH VIL VIH VIL tCCZ 50%OVDD VIH VIL ...
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... DTSCD bit sets to “0” until no-PCM bitstream is detected again. The ORed value of NPCM and DTSCD bits are output to AUTO bit. The AK4115 detects the 14-bit sync word and the 16-bit sync word of a DTS-CD bitstream, the detection function can be set ON/OFF by DTS14 and DTS16 bits in serial mode. In parallel mode, the logical OR value of the AUTO and DTS-CD bits are outputted to the INT1 pin ...
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... The PLL lock range is 22kHz to 216kHz. The word clock (ELRCK pin) can receive signal levels of 0.5Vpp(min) when AC coupled. In master mode, the clock phase between ELRCK pin and LRCK pin is within ± 5%. When the AK4115 is supplied with a bi-phase signal and a word clock (ELRCK), the phase error between the LRCK and ELRCK is within ± ...
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... XSEL Oscillator Clock Selector Clock Recovery (CM1-0) DEM DAIF Decoder XTI1 XTO1 ACKS X'tal XSEL Oscillator Clock Selector Clock Recovery (CM1- [AK4115] XTI2 XTO2 X'tal Oscillator MCKO1 Clock MCKO2 Generator LRCK Audio I/F BICK for RX/TX SDTO DAUX XTI2 XTO2 X'tal Oscillator MCKO1 ...
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... Note 20 (RX X'tal Note X'tal Note 20 XTI1 XTO1 X'tal XSEL Oscillator Clock Selector Clock Recovery (CM1-0) DEM DAIF Decoder - 19 - [AK4115] TX Clock Clock SDTO I/O Source I/O X’tal or RX Note 21 EMCK (Note 22) X’tal “L” or Note 21 EMCK X’tal RX or Note 21 EMCK X’ ...
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... Block start, Channel status bit, User bit and Validity bit The AK4115 can control and monitor block start, channel status bits, user bits and validity bit for RX and TX and U pins are bi-directional and the direction of input/output can be selected by the BCU_IO bit and VOUT pins become “ ...
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... SDTO pin SDTO pin (Note 30) (Note 31) RX User bit Validity bit Channel Status bit Default value of U pin VOUT pin CT191-0 bits - 21 - [AK4115] TX Channel Validity User bit Status bit bit C pin VIN pin CT191-0 bits U pin VTX bit (Note 32) (Note 34) ...
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... TX. When CTX bit is set to “1”, the values of CT191-0 bits are outputted with audio data from TX. When the CCRE bit is “1” and AK4115 is in professional mode (bit0 = “1”), the CRC code can be generated according to the professional mode definition in the AES3 standard. When the CCRE bit is “0”, the CRC data is not generated and the data from the CT191-0 bits is passed to the TX directly. In the consumer mode (bit0 = “ ...
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... The input to B pin is ignored in AES3 mode and the B bit on DAUX is used as the block start timing. B (Input) B (Output) C(R191) C (or U,V) LRCK(ELRCK) 2 (Except I S) LRCK(ELRCK SDTO (DAUX) R191 MS0573-E-00 Don’t care C(L0) C(R0) C(L1 Figure 17 Input/output timings - 23 - [AK4115] Don’t care C(L38) C(R39) C(L40) L38 R39 L40 2006/12 ...
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... ASAHI KASEI Master Clock Output The AK4115 has two master clock outputs, MCKO1 and MCKO2. MCKO2 has two modes. These modes can be selected by the XMCK bit. 1) When XMCK bit = “0” These clocks are derived from either the recovered clock or the X'tal oscillator. The frequencies of the master clock outputs (MCKO1 and MCKO2) are set by OCKS0 and OCKS1 as shown in Table 9 ...
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... ASAHI KASEI X’tal Oscillator The AK4115 has two X’tal oscillators. They can not operate at the same time. The operation of the X’tal oscillator is selected by the XSEL bit or the XSEL pin. XSEL 0 1 The following circuits are available to feed the clock to the XTI1/2 pins of AK4115. ...
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... ASAHI KASEI Sampling Frequency and Pre-emphasis Detection The AK4115 has two methods for detecting the sampling frequency: 1. Clock comparison between the recovered clock and X’tal oscillator 2. Sampling frequency information from channel status The method is selected by the XTL1,0 pins. When XTL1 “1,1”, the sampling frequency is detected by the channel status sampling frequency information ...
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... The AK4115 is in this mode by default. In parallel control mode, the AK4115 is always placed in this mode and the status bits in channel 1 control the de-emphasis filter. In serial control mode, DEM0/1 bits control the de-emphasis filter when the DEAU bit is “0”. The internal de-emphasis filter is bypassed and the recovered data is available without any change if either the pre-emphasis or de-emphasis mode is OFF. When the PEM bit is “ ...
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... ASAHI KASEI System Reset and Power-Down The AK4115 has a power-down mode for all circuits by PDN pin and can be partially powerd-down by PWN bit. The RSTN bit initializes the register and resets the internal timing. In parallel mode, only the control by PDN pin is enabled. ...
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... ASAHI KASEI Bi-phase Output The AK4115 has two transmitter outputs, TX0 and TX1. TX0 is a loop-through output that is selected from the RX input. TX0 output is selected from RX7-0 by the OPS00, OPS01 and OPS02 bits. In parallel mode, the source of the loop-through output from TX0 is fixed to RX0. ...
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... RX input lines. In this case, a shield is recommended between the input lines. In parallel mode, RX3-0 is available and RX7-4 change to other pins for audio format control. Those pins must be fixed to “H” or “L”. MS0573-E-00 0.1uF 75 Ω 470 O/E 0.1uF 110Ω 0.1uF - 30 - [AK4115] RX AK4115 RX AK4115 RXP RXN AK4115 2006/12 ...
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... The output level of TX0 is 0.5V ± 20% using the external resistor network in consumer mode. R1 TX0 TVSS Note: When the AK4115 is in the power-down mode (PDN pin = “L”), power supply current can be reduced by using an AC coupling capacitor as shown in Figure 24, since TX1 output is undetermined in power-down mode. 0.1uF TX0 TVSS 2 ...
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... R2 T1 AK4115 FILT AVSS Figure 27. PLL Loop Filter C1 [nF] C2 [pF] R [Ω] 24k ± ± 30% 100 ± 30% Table 24. Value of PLL Loop Filter - 32 - [AK4115] 75Ω cable TVDD R1 R2 3.3V 270Ω 150Ω 3.0V 240Ω 150Ω 5.0V 430Ω 150Ω 2006/12 ...
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... ASAHI KASEI Q-subcode buffers The AK4115 has a Q-subcode buffer for CD applications. The AK4115 takes the Q-subcode into registers by the following method. 1. The sync word (S0,S1) is constructed of at least 16 “0”s. 2. The start bit is “1”. 3. Those 7bits Q-W follows to the start bit. 4. The distance between two start bits are 8-16 bits. ...
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... Operation Mode 1), INT0 and INT1 pins go to “L”. 1. UNLCK : PLL unlock state detect “1” when the PLL loses lock. The AK4115 loses lock when the time between two preambles is not correct or when those preambles are not correct. 2. PAR : Parity error or bi-phase coding error detection “ ...
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... Once QINT, CINT and DAT bits go to “1”, it stays “1” until the register is read. When the AK4115 loses lock, the channel status bit, user bit, Pc and Pd are initialized. In this initial state, INT0 pin outputs the ORed signal between UNLCK and PAR bits. INT1 pin outputs the ORed signal between AUTO and AUDION bits ...
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... SDTO (PAR error) SDTO (others) VOUT pin (UNLOCK) VOUT pin (except UNLOCK) MS0573-E-00 (Error) Hold Time (max: 4096/fs) Hold Time = 0 Hold “1” READ 07,08H Free Run (fs: around 6kHz) Previous Data Figure 31. INT0/1 pin timing - 36 - [AK4115] Reset Normal Operation 2006/12 ...
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... Figure 32. Error Handling Sequence Example 1 MS0573-E-00 PDN pin ="L" to "H" Initialize Read (07H, 08H) INT0/1 pin ="H" No Yes Mute DA C output Read (07H, 08H) (Each Error Handling) Read 07H, 08H (Res ets registers) No INT0/1 pin ="H" Yes - 37 - [AK4115] 2006/12 ...
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... PDN pin ="L" to "H" Initialize Read (07H, 08H) INT1 pin ="H" No Yes Read (07H, 08H) and Detect QSUB= “1” (Read Q-buffer) No New data QCRC = “0” Yes No INT1 pin ="L" Yes New data is valid - 38 - [AK4115] is invalid 2006/12 ...
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... UNLCK : PLL unlock state detect “1” when the PLL loses lock. The AK4115 loses lock when the phase difference between the current ELRCK and the previous ELRCK is more than 5% after “4 x fs”. The PLL is locked when the phase difference between the current ELRCK and the pervious ELRCK is less than 2% after “ ...
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... Figure 34). When the Parity Error, Bi-phase Error or Frame Length Error occurs in a sub-frame, the AK4115 continues to output the last normal sub-frame data from SDTO repeatedly until the error is removed. When the Unlock Error occurs, AK4115 outputs “ ...
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... Table 29. Audio data format in parallel mode ELRCK DAUX 0 24bit, Left justified H 24bit L/H 0 24bit, Left justified H 24bit L/H ECKS0 EMCK Frequency 0 512fs 1 256fs 0 128fs 1 N/A Table 31. EMCK Frequency - 41 - [AK4115] LRCK BICK I/O H/L O 64fs H/L O 64fs H/L O 64fs H/L O 64fs H/L O 64fs L/H O 64fs H/L I 64-128fs L/H I 64-128fs H/L O 64fs ...
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... Mode4 : LRCK, BICK, ELRCK, EBICK : Output Mode6 : LRCK, BICK, ELRCK, EBICK: Input Lch Data Mode5 : LRCK, BICK, ELRCK, EBICK : Output Mode7 : LRCK, BICK, ELRCK, EBICK : Input - 42 - [AK4115 Rch Data ...
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... CSN. For read operations, the CDTO output goes high impedance after a low-to-high transition of CSN. The maximum speed of CCLK is 5MHz. PDN pin = “L” resets the registers to their default values. When the state of P/SN pin is changed, the AK4115 should be reset by PDN pin = “L”. CSN should be brought “H” after each word. ...
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... C-bus system (max : 400kHz). 2-1. Data transfer All commands are preceded by a START condition. After the START condition, a slave address is sent. After the AK4115 recognizes the START condition, the device interfaced to the bus waits for the slave address to be transmitted over the SDA line ...
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... In the read mode, the slave, AK4115 will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge acknowledge is detected and no STOP condition is generated by the master, the slave will continue to transmit data ...
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... The AK4115 is capable of more than one byte write operation by one sequence. After receipt of the third byte, the AK4115 generates an acknowledge, and awaits the next data again. The master can transmit more than one word instead of terminating the write cycle after the first data word is transferred. After the receipt of each data, the internal 5-bit address counter is incremented by one, and the next data is taken into next address automatically. If the address exceed 49H prior to generating the stop condition, the address counter will “ ...
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... Therefore, if the last access (either a read or write) was to address n, the next CURRENT READ operation would access data from the address n+1. After receipt of the slave address with R/W bit set to “1”, the AK4115 generates an acknowledge, transmits 1byte data which address is set by the internal address counter and increments the internal address counter the master does not generate an acknowledge to the data but generate the stop condition, the AK4115 discontinues transmission ...
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... Q57 Q56 Q55 Q54 Q65 Q64 Q63 Q62 Q73 Q72 Q71 Q70 Q81 Q80 Q79 Q78 [AK4115 OCKS1 OCKS0 PWN RSTN DEAU DEM1 DEM0 ACKS TX0E OPS02 OPS01 OPS00 DIT IPS2 IPS1 IPS0 MV0 MSTC0 MAUD0 MPAR0 ...
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... DIF2-0, AES3: Audio Data Format Control (See Table 28) MS0573-E- CS12 BCU CM1 CM0 R/W R/W R/W R AES3 DIF2 DIF1 DIF0 R/W R/W R/W R [AK4115 OCKS1 OCKS0 PWN RSTN R/W R/W R/W R DEAU DEM1 DEM0 ACKS R/W R/W R/W R 2006/12 ...
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... LRCK MS0573-E- TX1E OPS12 OPS11 OPS10 TX0E R/W R/W R/W R EFH1 EFH0 UDIT BCU_IO R/W R/W R/W R 01: 1024 LRCK (Default) 11: 4096 LRCK - 50 - [AK4115 OPS02 OPS01 OPS00 R/W R/W R/W R DIT IPS2 IPS1 IPS0 R/W R/W R/W R 2006/12 ...
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... MQIT0: Mask enable for QINT bit 0: Mask disable 1: Mask enable (Default) When mask is set to “1”, corresponding event does not affect INT0 pin operation. MS0573-E- MQIT0 MAUT0 MCIT0 MULK0 MVRX0 MSTC0 MAUD0 MPAR0 R/W R/W R/W R [AK4115 R/W R/W R/W R 2006/12 ...
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... MAUT1:Mask enable for AUTO bit 0: Mask disable (Default) 1: Mask enable MQIT1: Mask enable for QINT bit 0: Mask disable 1: Mask enable (Default) When mask is set to “1”, corresponding event does not affect INT1 pin operation. MS0573-E- R/W R/W R/W R [AK4115 R/W R/W R 2006/12 ...
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... Fixed to X’tal Mode DIV: MCKO2 Output Frequency Select at X’tal Mode (See Table 10) 0: Same frequency as X’tal (Default) 1: Half frequency of X’tal MS0573-E- DIV XMCK FAST DCNT R/W R/W R/W R [AK4115 DTS16 DTS14 MDAT1 MDAT0 R/W R/W R/W R 2006/12 ...
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... This bit goes to “1” when Q-subcode stored in register addresses 40H to 49H changes. STC, QINT, CINT and PAR bits are initialized when 07H is read. MS0573-E- QINT AUTO CINT UNLCK [AK4115 VRX STC AUDION PAR 2006/12 ...
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... Error MS0573-E- FS3 FS2 FS1 FS0 [AK4115 PEM DAT DTSCD NPCM QCRC CCRC 2006/12 ...
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... MSEL: Master clock setting for TX in asynchronous mode (See Table 4) MS0573-E- MCK1E MCK1E ASYNC RD R/W R ECKS1 ECKS0 EDIF1 EDIF0 RD RD R/W R [AK4115 WSYNC XSEL PSEL R/W R/W R/W R CTRAN CCRE VTX R/W R/W R/W R ...
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... CT191 CT190 CT189 CT188 CT187 CT186 CT185 CT184 R PC7 PC6 PC5 PC4 PC15 PC14 PC13 PC12 PD7 PD6 PD5 PD4 PD15 PD14 PD13 PD12 RD Not initialized - 57 - [AK4115 CR3 CR2 CR1 CR0 • • • • CT3 CT2 CT1 CT0 CT11 ...
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... Q73 Q72 Q71 Q70 Q81 Q80 Q79 Q78 Not initialized [AK4115 Q13 Q12 Q11 Q10 Q21 Q20 Q19 Q18 Q29 Q28 Q27 Q26 Q37 Q36 Q35 Q34 Q45 Q44 ...
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... Figure 50. Data structure in IEC60958 Contents sync word 1 sync word 2 Burst info Length code Table 32. Burst preamble words Table 33. Fields of burst info [AK4115 MSB stuffing Value 0xF872 0x4E1F see Table 33 numbers of bits Repetition time of burst in IEC60958 frames ≤ ...
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... Repetition time >4096 frames Figure 51. Timing example 1 < PLL Lock time Stop 2~3 Syncs (B Figure 52. Timing example [AK4115 INT0 hold time <Repetition time ...
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... Top View S/PDIF out 5V 3. [AK4115 4.7µ + 10kΩ 100p 10n 24kΩ FILT 48 XTL1 47 XTL0 46 PSEL 45 IIC 44 BVSS 43 DVSS 3.3V DVDD 41 CSN 40 CCLK 39 CDTI ...
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... ASAHI KASEI 64pin LQFP(Unit:mm) 12.0 ± 0.3 10 0.22 ± 0.05 0.5 0.10 Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: Solder (Pb free) plate MS0573-E-00 PACKAGE 1.70MAX 33 1. 0.10 M 0° ∼ 10° 0.5 ± 0.2 Epoxy [AK4115] 0.10 ± 0.05 +0.05 -0.05 0.17 ± 0.05 2006/12 ...
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... ASAHI KASEI 1 Date (YY/MM/DD) Revision Reason 06/12/13 00 First Edition MS0573-E-00 MARKING AKM AK4115VQ XXXXXXX XXXXXXX: Date code identifier Revision History Page Contents - 63 - [AK4115] 2006/12 ...
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... AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0573-E-00 IMPORTANT NOTICE - 64 - [AK4115] Before considering As 2006/12 ...