ak4127 AKM Semiconductor, Inc., ak4127 Datasheet
ak4127
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ak4127 Summary of contents
Page 1
... The output sample rate is from 8kHz to 216kHz. The system can take very simple configuration because the AK4127 has an internal PLL and does not need any master clock at slave mode. The AK4127 is suitable for the application interfacing to different sample rates such as high-end Car Audio and DVD recorder ...
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... Dither ........................................................................................................................................................................ 20 ■ System Reset ............................................................................................................................................................. 20 ■ Internal Reset Function for Clock Change ................................................................................................................ 21 ■ Sequence of Changing Clocks .................................................................................................................................. 21 ■ UNLOCK pin ............................................................................................................................................................ 21 ■ PLL Loop Filter......................................................................................................................................................... 22 SYSTEM DESIGN........................................................................................................................................................... 23 PACKAGE ....................................................................................................................................................................... 27 ■ Material & Lead finish .............................................................................................................................................. 27 MARKING ....................................................................................................................................................................... 28 REVISION HISTORY ..................................................................................................................................................... 28 IMPORTANT NOTICE ................................................................................................................................................... 29 MS0593-E-01 TABLE OF CONTENTS - 2 - [AK4127] 2007/07 ...
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... Ordering Guide −40 ∼ +85°C AK4127VF AKD4127 Evaluation Board for AK4127 ■ Pin Layout FILT AVSS PDN SMUTE DITHER PLL2 ILRCK IBICK SDTI IDIF0 IDIF1 IDIF2 PLL0 PLL1 UNLOCK MS0593-E-01 30pin VSOP (0.65mm pitch Top View ...
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... Compatibility with AK4125 Item TDM Mode Slave Mode at Bypass Mode OMCLK pin OMCLK=192fso for Output PORT (at Master Mode) MS0593-E-01 AK4125 AK4127 - - Normal Mode: OMCLK OMCLK TDM Mode: TDMIN X (-: Not available, X: Available [AK4127 2007/07 ...
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... Master Clock/TDM Data Input Pin for Output PORT OMCLK: Master Clock Input Pin (except for PLL2/1/0 pin = “L/H/H”) TDMIN: TDM Data Input Pin (PLL2/1/0 pin = “L/H/H”) Digital Power Supply Pin, 3.0 ∼ 3.6V Digital Ground Pin Analog Power Supply Pin, 3.0 ∼ 3. Function [AK4127] 2007/07 ...
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... This pin should be open. ABSOLUTE MAXIMUM RATINGS Symbol AVDD DVDD ΔGND (Note 2) IIN VIND Ta Tstg Symbol min AVDD 3.0 DVDD 3 min max −0.3 4.6 −0.3 4.6 - 0.3 ±10 - −0.3 DVDD+0.3 −40 85 −65 150 typ max 3.3 3.6 3.3 AVDD [AK4127] Units °C °C Units V V 2007/07 ...
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... Worst Case (FSO/FSI = 48kHz/32kHz) Dynamic Range (Input = 1kHz, −60dBFS, A-weighted, Note 5) FSO/FSI = 44.1kHz/48kHz Ratio between Input and Output Sample Rate Note 5. Measured by Audio Precision System Two Cascade MS0593-E-01 SRC CHARACTERISTICS Symbol FSI FSO FSO/FSI - 7 - [AK4127] min typ max Units 24 Bits 8 216 kHz 8 216 kHz − ...
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... SA 121.4 SA 115.3 SA 116.9 SA 114.6 SA 100.2 SA 103.3 SA 102.0 SA 103.6 SA 104.0 SA 103.3 SA 73.2 (Note [AK4127] typ max Units 0.4583FSI kHz 0.4167FSI kHz 0.3195FSI kHz 0.2852FSI kHz 0.2182FSI kHz 0.2177FSI kHz 0.1948FSI kHz 0.1458FSI kHz 0.1302FSI kHz 0.0917FSI kHz 0.0826FSI kHz 0.0583FSI kHz ...
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... DVDD−0 0.4 ± 100 10 100 typ max 41.472 8 216 216 [AK4127] Units μ μA Units MHz ns ns kHz % % kHz % % kHz 2007/07 ...
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... OBICK “↓” to OLRCK OBICK “↓” to SDTO Reset Timing PDN Pulse Width Note 8. BICK rising edge must not occur at the same time as LRCK edge. Note 9. The AK4127 can be reset by bringing the PDN pin = “L”. MS0593-E-01 fBCK dBCK −20 ...
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... Note : BICK shows IBICK and OBICK, LRCK shows ILRCK and OLRCK. MS0593-E-01 1/fCLK tCLKH tCLKL 1/fs tBCK tBCKH tBCKL Clock Timing tLRB tLRS tBSD tSDS tSDH Audio Interface Timing (Slave mode [AK4127] VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL 50%DVDD VIH VIL 2007/07 ...
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... LRCK tMBLR BICK SDTO SDTI Note : BICK shows IBICK and OBICK, LRCK shows ILRCK and OLRCK. PDN MS0593-E-01 tBSD tSDS tSDH Audio Interface Timing (Master mode) tPD Power Down & Reset Timing - 12 - [AK4127] 50%DVDD dBCK 50%DVDD 50%DVDD VIH VIL VIL 2007/07 ...
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... IBICK Freq IMCLK Depending Not on IDIF2-0 needed. ( Note 11) ( Note 13) ) 32fsi (Note 12) Not 64fsi needed Note 13) 128fsi 64fsi 128fsi 256fsi 512fsi 128fsi 64fsi 192fsi 384fsi 768fsi 192fsi [AK4127] Slave Master SMUTE ( Note 14) Manual Semi-Auto Manual Manual Semi-Auto Manual Semi-Auto Manual Semi-Auto 2007/07 ...
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... Lch Data Figure 3. Mode 2,5 Timing (24bit MSB Don't Care 23 22 Lch Data Figure 4. Mode 3, 6 Timing (24bit [AK4127 ...
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... OMCLK fso 8k ∼ 108kHz 256fso 8k ∼ 108kHz 384fso 8k ∼ 54kHz 512fso 8k ∼ 54kHz 768fso Not used. Set to DVSS. 8k ∼ 216kHz ( Note 15) 8k ∼ 216kHz 128fso Not used. Set to DVSS. 8k ∼ 216kHz ( Note 15) 8k ∼ 216kHz Not used. Set to DVSS. [AK4127] 1 2007/07 ...
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... Rch Data [AK4127] LSB justified 64fso ...
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... BICK 32 BICK 32 BICK 2 Figure 10. TDM mode I S Compatible Timing - [AK4127 2007/07 ...
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... Cascade TDM Mode The AK4127 supports cascading connection four devices (8channels daisy chain configuration at TDM mode. In this mode, the SDTO pin of device #N is connected to TDMIN pin of device #(N+1). The device can output up to 8ch TDM data multiplexed with TDMIN data. Figure 11shows a connection example of a daisy chain. ...
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... Semi-Auto mode The soft mute is cancelled automatically by the setting of PLL2-0 pins (Table 2), after the AK4127 detects the rising edge (PDN pin = “L” → “H”) and the mute is continued during 4410/fso=100ms@fso=44.1kHz. After PDN pin = “L” → “H” ...
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... Dither The AK4127 has a dither circuit. The dither circuit adds the dither to the LSB of the output data, which is the value of the OBIT1-0 pins, by DITHER pin = “H” regardless of the SRC mode or the SRC bypass mode. ■ System Reset Bringing the PDN pin = “L” sets the AK4127 power-down mode and initializes the digital filter. The AK4127 should be reset once by bringing the PDN pin = “ ...
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... Internal Reset Function for Clock Change The AK4127 is reset automatically when the output clock is stopped. If the output clock is started again, normal data is output within 100ms. ■ Sequence of Changing Clocks The change sequence of the clock supplied to AK4127 is shown in Figure 17 External clocks ...
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... Table 6. PLL Loop Filter (ILRCK Mode) PLL0 ILRCK R [Ω] 8k ∼ 216kHz 470 ± Table 7 are required [nF] C1 [μF] 0.68 ± 30% 0.68 ± 30% 1.0 ± 30% 2.2 ± 30% 0.68 ± 30% 0.68 ± 30% 1.0 ± 30% 2.2 ± 30% 0.68 ± 30% 0.68 ± 30% 1.0 ± 30% 2.2 ± 30% 0.68 ± 30% 0.68 ± 30% C2 [nF] C1 [μF] 0.22 ± 30% 1.0 ± 30 Compatible. Figure 18 are not required. [AK4127] 2007/07 ...
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... Reset fsi 64fsi DSP, uP Note: - AVSS and DVSS of the AK4127 must be distributed separately from the ground of external digital devices (MPU, DSP etc.). - All digital input pins must not be left floating. Figure 19. Typical Connection Diagram (Slave mode) MS0593-E-01 SYSTEM DESIGN 1 FILT ...
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... Grounding and Power Supply Decoupling The AK4127 requires careful attention to power supply and grounding arrangements. Alternatively if AVDD and DVDD are supplied separately, the power up sequence is not important. Decoupling capacitors should be as near to the AK4127 as possible, with the small value ceramic capacitor being the nearest. ...
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... When the ILRCK is generated by an external PLL, it may take time to settle after changing the input sampling frequency because the response of an external PLL to the frequency change is slow. The AK4127 operates normally up to 23%/sec speed but outputs incorrect data at the speed of the frequency change over 23%/sec. ...
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... Digital Filter Response Example Table 8shows the examples of digital filter response performed by the AK4127. Ratio FSO/FSI [kHz] 4.000 192/48.0 1.000 48.0/48.0 0.919 44.1/48.0 0.725 32.0/44.1 0.667 32.0/48.0 0.544 48.0/88.2 0.500 48.0/96.0 0.500 44.1/88.2 0.459 44.1/96.0 0.363 32.0/88.2 0.333 32.0/96.0 0.250 48.0/192.0 0.250 44.1/176.4 0.230 44.1/192.0 0.167 32.0/192.0 0.181 32.0/176.4 0.167 8/48.0 0.181 8/44 ...
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... VSOP (Unit: mm) *9.7 ± 0.1 0 0.22 ± 0.1 0.12 M NOTE: Dimension "*" does not include mold flash. ■ Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: MS0593-E-01 PACKAGE 16 15 0.65 Detail A 0.08 Epoxy Cu Solder (Pb free) plate - 27 - [AK4127] 1.5MAX A +0.10 0.15 -0.05 2007/07 ...
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... Revision 07/02/07 00 07/07/26 01 MS0593-E-01 MARKING AKM AK4127VF XXXBYYYYC XXXBYYYYC Date code identifier REVISION HISTORY Reason Page Contents First edition Description 19 Figure 13 and Figure 14 were changed. Change ■ Internal Rest Function for Clock Change 21 ■ Sequence of Changing Clocks ■ UNLOCK pin - 28 - [AK4127] 2007/07 ...
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... AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification. MS0593-E-01 IMPORTANT NOTICE , and AKEMD assumes no responsibility for such use, except for the use Note2 [AK4127] in any safety, life support, or Note1) 2007/07 ...