ak4121 AKM Semiconductor, Inc., ak4121 Datasheet
ak4121
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ak4121 Summary of contents
Page 1
... The output sample rate is 32kHz, 44.1kHz, 48kHz or 96kHz. Using the AK4121 simplifies system design, since the AK4121’s internal PLL eliminates the need for a master clock in slave mode. Then the AK4121 is suitable for applications requiring multiple sample rates, such as Car Audio, DVD recorders, and digital audio recording ...
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... DEM0 5 DEM1 6 ILRCK 7 IBICK 8 SDTI 9 IDIF0 10 IDIF1 11 IDIF2 12 T Major Difference between AK4120 and AK4121 Items MCLK Input Input sample rate (max) Vdd Input 5V Tolerant De-emphasis Filter Soft Mute Digital Volume Digital Mixer MS0191-E-03 24pin VSOP (0.65mm pitch ...
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... PIN/FUNCTION Function Loop-Filter Pin for PLL Analog Ground Pin Power-Down pin When “L”, the AK4121 is powered-down and reset. Soft Mute Pin De-emphasis Filter Control Pin #0 De-emphasis Filter Control Pin #1 L/R Clock Pin for Input Audio Serial Data Clock Pin for Input ...
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... Note 5. The “6” is the ratio when FSI is 8kHz and FSO is 48kHz. MS0191-E-03 ABSOLUTE MAXIMUM RATINGS Symbol min VDD 0.3 TVDD 0.3 GND IIN - VIN 0 Tstg 65 Symbol min VDD 3.0 TVDD VDD SRC PERFORMANCE Symbol FSI FSO FSO/FSI - 4 - [AK4121] max Units 4.6 V 6 TVDD+0 150 C typ max Units 3.3 3 5.5 V min typ max Units ...
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... SB 0.1822FSI (Note CHARACTERISTICS Symbol min (Note 7) VIH 0.7xVDD VIL - VOH VDD-0.4 VOL - Iin - - 5 - [AK4121] typ max Units 0.4583FSI kHz 0.4167FSI kHz 0.3195FSI kHz 0.2852FSI kHz 0.2245FSI kHz 0.2003FSI kHz 0.1781FSI kHz 0.1092FSI kHz kHz kHz kHz kHz kHz ...
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... Power-down & Reset Timing PDN Pulse Width Note 8. Min is 8kHz when BYPASS=“H”. Note 9. BICK rising edge must not occur at the same time as LRCK edge. Note 10. The AK4121 must be reset by bringing PDN “L” to “H” upon power-up. MS0191-E-03 SWITCHING CHARACTERISTICS =20pF) ...
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... SDTO SDTI MS0191-E-03 1/fCLK tCLKH tCLKL dCLK=tCLKH x fCLK, tCLKL x fCLK 1/fs tBCK tBCKH tBCKL Clock Timing tLRB tSDS tSDH Audio Interface Timing at Slave Mode - 7 - [AK4121] VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL tBSD 70%VDD 30%VDD VIH VIL 2004/08 ...
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... ASAHI KASEI LRCK tMBLR BICK SDTO tPD PDN Note: BICK means IBICK and OBICK. LRCK means ILRCK and OLRCK. MS0191-E-03 dBCK Audio Interface Timing at Master Mode Power-down & Reset Timing - 8 - [AK4121] 50%VDD 50%VDD tBSD 50%VDD VIH VIL 2004/08 ...
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... SDTO Format OBICK (Slave) 16bit LSB Justified 20bit LSB Justified 20/16bit MSB Justified 40fs or 32fs 2 20/16bit I S Compatible 40fs or 32fs Table 3. Output Audio Data Formats - 9 - [AK4121] Master/Slave (Output Port) Master Master Master Master Slave (Reserved) (Reserved) Master (BYPASS mode) IBICK (Slave) 32fs ...
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... Don’t care 19 18 Lch Data 2 Figure Timing - 10 - [AK4121 ...
Page 11
... DEM0 and DEM1. MS0191-E-03 , the attenuation is discontinued and returns to 0dB. (1) (1) after starting the operation, the attenuation is discontinued Figure 4. Soft Mute DEM1 DEM0 Mode 0 0 44.1kHz Default 0 1 OFF 1 0 48kHz 1 1 32kHz Table 4. De-emphasis Filter Control - 11 - [AK4121] dB during 1024 OLRCK cycles. (2) 2004/08 ...
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... ASAHI KASEI T System Reset Bringing the PDN=“L” places the AK4121 in power-down mode and initializes the digital filter. The AK4121 should be reset once by bringing PDN=“L” upon power-up. Regarding the SDTO valid time, please refer following table. Until then, the SDTO outputs “L”. ...
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... SDTO to remain “0”. 2. SMUTE can also be used to remove the unknown data. MS0191-E-03 (unknown) state 2 < 10msec < 100msec Power PLL locktime normal operation down & fs detection Note1 normal data 1024/fso Figure 6. Sequence of changing clocks - 13 - [AK4121] 2004/08 ...
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... The AK4121 requires careful attention to power supply and grounding arrangements. VDD are usually supplied from the system’s analog supply. AVSS and DVSS of the AK4121 must be connected to the analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board ...
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... ASAHI KASEI T Jitter Tolerance Figure 8 shows the jitter tolerance to ILRCK for AK4121. The jitter frequency and the jitter amplitude shown in Figure 8 define the jitter quantity. When the jitter amplitude is 0.01Uipp or less, the AK4121 operate normally regardless of the jitter frequency. 10.00 1.00 (2) 0.10 0.01 0.00 1 (1) Normal operation (2) There is a possibility that the distortion degrades ...
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... VDD FILT 0.1u AVSS DVSS PDN TVDD SMUTE MCLK DEM0 OLRCK AK4121 OBICK DEM1 ILRCK SDTO IBICK ODIF1 ODIF0 SDTI CMODE2 IDIF0 IDIF1 CMODE1 CMODE0 IDIF2 - 16 - [AK4121] +3.3V Analog +3.3~5V Digital (note 1) fso DSP2 +3.3V Analog +3.3~5V Digital (note 1) 256fso fso 64fso DSP2 2004/08 ...
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... ASAHI KASEI 24pin VSOP (Unit: mm) *7.9 0 0.22 0.1 Seating Plane 0.10 NOTE: Dimension "*" does not include mold flash. T Package & Lead frame material Package molding compound: Lead frame material: Lead frame surface treatment: MS0191-E-03 PACKAGE 0.65 Detail A Epoxy Cu Solder plate (Pb free [AK4121] 1.25 0.2 +0.1 0.15 -0.05 0.1 0.1 0-10 2004/08 ...
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... Values of external elements are changed. Condition 12 15 for data valid time is changed. Add Spec 6 SWITCHING CHARACTERISTICS Audio Interface Timing IBICK Period : min 160ns OBICK Period : min 160ns Add Spec 5 Add FILTER CHARACTERISTICS Add Spec 15 Add Jitter Tolerance - 18 - [AK4121] 1/64fs 1/64fs 2004/08 ...
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... AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0191-E-03 IMPORTANT NOTICE - 19 - [AK4121] 2004/08 ...