ak4125 AKM Semiconductor, Inc., ak4125 Datasheet
ak4125
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ak4125 Summary of contents
Page 1
... The output sample rate is from 8kHz to 216kHz. The system can take very simple configuration because the AK4125 has an internal PLL and does not need any master clock at slave mode. The AK4125 is suitable for the application interfacing to different sample rates such as high-end Car Audio and DVD recorder ...
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... Ordering Guide −40 ∼ +85°C AK4125VF AKD4125 Evaluation Board for AK4125 ■ Pin Layout FILT AVSS PDN SMUTE DITHER PLL2 ILRCK IBICK SDTI IDIF0 IDIF1 IDIF2 PLL0 PLL1 UNLOCK MS0379-E-04 30pin VSOP (0.65mm pitch Top View ...
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... FSO/FSI < 0.452 0.1212FSI 0.324 ≤ FSO/FSI < 0.357 0.1072FSI 0.246 ≤ FSO/FSI < 0.324 0.0595FSI 0.226 ≤ FSO/FSI < 0.246 0.0484FSI 0.1667 ≤ FSO/FSI < 0.226 0.0182FSI - 3 - [AK4125] AK4125 ← ← ← ← ← 0.2177FSI 0.1948FSI 0.1458FSI 0.1302FSI 0.0917FSI 0.0826FSI 0.0583FSI 2007/07 ...
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... Audio Serial Data Output Pin for Output PORT Audio Serial Data Clock Pin for Output PORT Output Channel Clock Pin for Output PORT Master Clock Input Pin for Output PORT Digital Power Supply Pin, 3.0 ∼ 3.6V Digital Ground Pin Analog Power Supply Pin, 3.0 ∼ 3. Function [AK4125] 2007/07 ...
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... This pin should be open. ABSOLUTE MAXIMUM RATINGS Symbol AVDD DVDD ΔGND (Note 2) IIN VIND Ta Tstg Symbol min AVDD 3.0 DVDD 3 min max −0.3 4.6 −0.3 4.6 - 0.3 ±10 - −0.3 DVDD+0.3 −40 85 −65 150 typ max 3.3 3.6 3.3 AVDD [AK4125] Units °C °C Units V V 2007/07 ...
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... Worst Case (FSO/FSI = 48kHz/32kHz) Dynamic Range (Input = 1kHz, −60dBFS, A-weighted, Note 4) FSO/FSI = 44.1kHz/48kHz Ratio between Input and Output Sample Rate Note 4. Measured by Audio Precision System Two Cascade. MS0379-E-04 SRC CHARACTERISTICS Symbol FSI FSO FSO/FSI - 6 - [AK4125] min typ max Units 24 Bits 8 216 kHz 8 216 kHz − ...
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... SA 121.4 SA 115.3 SA 116.9 SA 114.6 SA 100.2 SA 103.3 SA 102.0 SA 103.6 SA 104.0 SA 103.3 SA 73.2 (Note [AK4125] typ max Units 0.4583FSI kHz 0.4167FSI kHz 0.3195FSI kHz 0.2852FSI kHz 0.2182FSI kHz 0.2177FSI kHz 0.1948FSI kHz 0.1458FSI kHz 0.1302FSI kHz 0.0917FSI kHz 0.0826FSI kHz 0.0583FSI kHz ...
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... Note 6. All digital input pins are held DVSS. MS0379-E-04 DC CHARACTERISTICS Symbol VIH VIL (Iout=−400μA) VOH (Iout=400μA) VOL Iin AVDD=DVDD=3.3V : AVDD=DVDD=3.6V (Note min typ max 70%DVDD - - - - 30%DVDD DVDD−0 0.4 ± 100 [AK4125] Units μ μA 2007/07 ...
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... OBICK “↓” to OLRCK OBICK “↓” to SDTO Reset Timing PDN Pulse Width Note 7. BICK rising edge must not occur at the same time as LRCK edge. Note 8. The AK4125 can be reset by bringing the PDN pin = “L”. MS0379-E-04 SWITCHING CHARACTERISTICS =20pF) L ...
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... Note: BICK shows IBICK and OBICK, LRCK shows ILRCK and OLRCK. MS0379-E-04 1/fCLK tCLKH tCLKL 1/fs tBCK tBCKH tBCKL Clock Timing tLRB tLRS tBSD tSDS tSDH Audio Interface Timing (Slave mode [AK4125] VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL 50%DVDD VIH VIL 2007/07 ...
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... LRCK tMBLR BICK SDTO SDTI Note: BICK shows IBICK and OBICK, LRCK shows ILRCK and OLRCK. PDN MS0379-E-04 tBSD tSDS tSDH Audio Interface Timing (Master mode) tPD Power Down & Reset Timing - 11 - [AK4125] 50%DVDD dBCK 50%DVDD 50%DVDD VIH VIL VIL 2007/07 ...
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... IBICK Freq IMCLK Depending on Not IDIF2-0 needed. ( Note 10) ( Note 12) Reserved 32fsi (Note 11) Not 64fsi needed. 128fsi ( Note 12) 64fsi 128fs 256fs 512fs 128fs 64fs 192fs 384fs 768fs 192fs [AK4125] Slave Master SMUTE ( Note 13) Manual Semi-Auto Manual Semi-Auto Manual Semi-Auto Manual Semi-Auto 2007/07 ...
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... Lch Data Figure 3. Mode 2,5 Timing (24bit MSB Don't Care 23 22 Lch Data Figure 4. Mode 3, 6 Timing (24bit [AK4125 ...
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... Not used. Set to DVSS. 8k ∼ 216kHz 128fso 8k ∼ 216kHz 192fso 8k ∼ 216kHz Not used. Set to DVSS. OBICK Frequency OBICK 2 MSB justified LSB justified ≥ 32fso ≥ 36fso Input ≥ 40fso ≥ 48fso Output 64fso [AK4125] 1 64fso 2007/07 ...
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... Rch Data [AK4125 ...
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... Semi-Auto mode The soft mute is cancelled automatically by the setting of PLL2-0 pins (Table 2), after the AK4125 detects the rising edge (PDN pin = “L” → “H”) and the mute is continued during 4410/fso=100ms@fso=44.1kHz. After PDN pin = “L” → “H” ...
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... Dither The AK4125 has a dither circuit. The dither circuit adds the dither to the LSB of the output data, which is the value of the OBIT1-0 pins, by DITHER pin = “H” regardless of the SRC mode or the SRC bypass mode. ■ System Reset Bringing the PDN pin = “L” sets the AK4125 power-down mode and initializes the digital filter. The AK4125 should be reset once by bringing the PDN pin = “ ...
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... Internal Reset Function for Clock Change The AK4125 is reset automatically when the output clock is stopped. If the output clock is started again, normal data is output within 100ms. ■ Sequence of Changing Clocks The change of the clock supplied to AK4125 is shown in Figure 13 External clocks (Input port ...
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... Table 6. PLL Loop Filter (ILRCK Mode) PLL0 ILRCK R [Ω] 8k ∼ 216kHz 470 ± Table 7 are required [nF] C1 [μF] 0.68 ± 30% 0.68 ± 30% 1.0 ± 30% 2.2 ± 30% 0.68 ± 30% 0.68 ± 30% 1.0 ± 30% 2.2 ± 30% 0.68 ± 30% 0.68 ± 30% C2 [nF] C1 [μF] 0.22 ± 30% 1.0 ± 30 Compatible. Figure 14 are not required. [AK4125] 2007/07 ...
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... Reset fsi 64fsi DSP, uP Note: - AVSS and DVSS of the AK4125 should be distributed separately from the ground of external digital devices (MPU, DSP etc.). - All digital input pins should not be left floating. Figure 15. Typical Connection Diagram (Slave mode) MS0379-E-04 SYSTEM DESIGN 1 FILT ...
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... Grounding and Power Supply Decoupling The AK4125 requires careful attention to power supply and grounding arrangements. Alternatively if AVDD and DVDD are supplied separately, the power up sequence is not important. Decoupling capacitors should be as near to the AK4125 as possible, with the small value ceramic capacitor being the nearest. ...
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... When the ILRCK is generated by an external PLL, it may take time to settle after changing the input sampling frequency because the response of an external PLL to the frequency change is slow. The AK4125 operates normally up to 23%/sec speed but outputs incorrect data at the speed of the frequency change over 23%/sec. ...
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... Digital Filter Response Example Table 8 shows the examples of digital filter response performed by the AK4125. Ratio FSO/FSI [kHz] 4.000 192/48.0 1.000 48.0/48.0 0.919 44.1/48.0 0.725 32.0/44.1 0.667 32.0/48.0 0.544 48.0/88.2 0.500 48.0/96.0 0.500 44.1/88.2 0.459 44.1/96.0 0.363 32.0/88.2 0.333 32.0/96.0 0.250 48.0/192.0 0.250 44.1/176.4 0.230 44.1/192.0 0.167 32.0/192.0 0.181 32.0/176.4 0.167 8/48.0 0.181 8/44 ...
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... VSOP (Unit: mm) *9.7 ± 0.1 0 0.22 ± 0.1 0.12 M NOTE: Dimension "*" does not include mold flash. ■ Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: MS0379-E-04 PACKAGE 16 15 0.65 Detail A 0.08 Epoxy Cu Solder (Pb free) plate - 24 - [AK4125] 1.5MAX A +0.10 0.15 -0.05 2007/07 ...
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... FSO/FSI = 48kHz/8kHz Error 9 Switching Characteristics (ILRCK) Correction Master/Slave modes were added to Duty Cycle. 20,21 Connections of PLL1/PLL0 pins were corrected. Description 16 Figure 9 and Figure 10 were changed. Change 18 ■ Internal Rest Function for Clock Change ■ Sequence of Changing Clocks ■ UNLOCK pin - 25 - [AK4125] 32kHz/176.4kHz 2007/07 ...
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... AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification. MS0379-E-04 IMPORTANT NOTICE , and AKEMD assumes no responsibility for such use, except for the use Note2 [AK4125] in any safety, life support, or Note1) 2007/07 ...