ak4104 AKM Semiconductor, Inc., ak4104 Datasheet - Page 10

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ak4104

Manufacturer Part Number
ak4104
Description
192khz 24-bit 3.3v Dit
Manufacturer
AKM Semiconductor, Inc.
Datasheet

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For correct synchronization, MCLK and LRCK should be derived from the same clock signal either directly (as through a
frequency divider) or indirectly (for example, as through a DSP). The phase relationship between MCLK and LRCK
should be kept after power-up. The MCLK frequencies shown in Table 1 are supported. The internal clock frequency is
set depending on the external MCLK frequency automatically.
MS0642-E-00
The AK4104 should be reset once by bringing PDN = “L” upon power-up. It takes 8 bit clock cycles for the AK4104 to
initialize after PDN pin goes “H”.
Reset and Initialization
MCLK and LRCK Relationship
OPERATION OVERVIEW
Table 1. MCLK Frequency
MCLK
1024fs
1536fs
128fs
192fs
256fs
384fs
512fs
768fs
- 10 -
16k-192kHz
16k-192kHz
8k-128kHz
8k-96kHz
8k-48kHz
8k-48kHz
8k-32kHz
8k-24kHz
Fs
2007/07

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