ak4145 AKM Semiconductor, Inc., ak4145 Datasheet

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ak4145

Manufacturer Part Number
ak4145
Description
Digital Stereo Btsc Encoder
Manufacturer
AKM Semiconductor, Inc.
Datasheet

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The AK4145 is a BTSC Encoder with D/A Converter, which is optimized for Digital AV application. The
AK4145 achieves high audio performance using the digital BTSC encoding architecture requires no
alignment of external parts. The AK4145 supports major audio data formats (MSB justified, I
interface with usual DSP. Therefore, the AK4145 is suitable for the systems such as Digital STB/TV,
digital recorder.
Rev. 0.3
FS1/SDA
DIF/SCL
LRCK
SDTI
BICK
Interface
Audio
Interface
Data
P/S
µP
Alignment Free Digital BTSC Stereo Encoding
Base band Composite Audio Output (Mono/Stereo)
Digital Volume for Composite Audio Output
Digital De-emphasis filter (32k/44.1k/48kHz)
Stereo Digital Volume Control for Audio Input Data
Soft Mute
Sampling Rate (fs): 32k/44.1k/48kHz
Master Clock: 256fs/384fs/512fs/768fs
I/F format: 24-Bit MSB justified, 24/20/16-Bit LSB justified or I
Control: Standalone/I
Video Input for Pilot Synchronization
S/(N+D): 0.01%
S/N: 82dB
Channel Separation: 47dB
Power Supply: 1.7V ~ 1.9V, 2.7 ~ 3.6V
Ta: -20 ~ 85°C
De-emphasis,
Stereo Matrix
DVOL,
GENERAL DESCRIPTION
PDN
= Preliminary =
FEATURES
2
C-bus Selectable
- 1 -
Encoder
Digital
BTSC
Digital BTSC Stereo Encoder
MCLK
PLL
DATT
FILT
AK4145
separator
Sync
DAC
2
2
S
S, TDM) to
[AK4145]
2007/11
CA
TVDD
DVDD
VSS
VCOM
AVDD
CV/27M

Related parts for ak4145

ak4145 Summary of contents

Page 1

... The AK4145 is a BTSC Encoder with D/A Converter, which is optimized for Digital AV application. The AK4145 achieves high audio performance using the digital BTSC encoding architecture requires no alignment of external parts. The AK4145 supports major audio data formats (MSB justified, I interface with usual DSP. Therefore, the AK4145 is suitable for the systems such as Digital STB/TV, digital recorder ...

Page 2

... Ordering Guide -20 ∼ +85°C AK4145ET AKD4145 Evaluation Board ■ Pin Layout FILT PSN CV27M PDN MCLK LRCK BICK SDTI Rev. 0.3 16pinTSSOP Top View [AK4145 AVDD 15 VCOM 14 13 VSS 12 DVDD 11 TVDD 10 DIF/SCL FS/SDA 9 2007/11 ...

Page 3

... Serial control mode, “H”: Parallel control mode 3 CV27M I Composite Video or 27MHz Signal Input Pin. 4 PDN I Power-Down Mode Pin When at “L”, the AK4145 is in the power-down mode and is held in reset. The AK4145 must be reset once upon power-up. 5 MCLK I Master Clock Input Pin 6 LRCK I ...

Page 4

... Parameter Power Supply WARNING: AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet. Rev. 0.3 ABSOLUTE MAXIMUM RATINGS Symbol AVDD DVDD TVDD IIN VIND Ta Tstg Symbol min AVDD 2.7 DVDD 1.7 TVDD DVDD - 4 - [AK4145] min max Units -0.3 4.3 V -0.3 2.4 V -0.3 4.3 V ± -0.3 TVDD+0.3 V °C -20 85 ° ...

Page 5

... Note 5. Received by the Belar TVM230 (BTSC Decoder) and measured by the Audio Precision (System Two). Refer to the evaluation board manual. Rev. 0.3 ANALOG CHARACTERISTICS min (Note 100 (Note [AK4145] typ max Units 16 Bits 2.2 Vp-p kΩ 0.01 TBD % 0.01 TBD % ...

Page 6

... PDN Pulse Width Note 6. BICK rising edge must not occur at the same time as LRCK edge. Note 7. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. Note 8. The AK4145 can be reset by bringing the PDN pin = “L”. 2 Note registered trademark of Philips Semiconductors. ...

Page 7

... LRCK BICK tBCKH LRCK tBLR BICK SDTI Rev. 0.3 1/fCLK tCLKL 1/fs tBCK tBCKL Figure 1. Clock Timing tLRB tSDS tSDH Figure 2. Serial Interface Timing - 7 - [AK4145] VIH VIL dCLK=tCLKH x fCLK, tCLKL x fCLK VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL 2007/11 ...

Page 8

... SDA tLOW tBUF SCL tHD:STA Stop Start PDN Rev. 0.3 tR tHIGH tF tHD:DAT tSU:DAT tSU:STA Start 2 Figure Bus mode Timing tPD Figure 4. Power-down Timing - 8 - [AK4145] VIH VIL tSP VIH VIL tSU:STO Stop VIL 2007/11 ...

Page 9

... Device power down. All registers are initialized. ■ Audio Sampling Rate The AK4145 supports 3 sampling rates as 32kHz, 44.1kHz and 48kHz. The FS1-0 bits select the sampling rate in serial control mode. The FS1 pin is only available in parallel control mode without the reset by the PDN pin. ...

Page 10

... The external clocks required to operate the AK4145 are MCLK, LRCK and BICK. The AK4145 supports 256fs, 384fs, 512fs and 768fs as master clock (MCLK). The AK4145 should be reset by the PDN pin = “L” after these clocks are provided. After exiting reset by the PDN pin = “H”, the AK4145 remains in power-down mode until the input of LRCK= “ ...

Page 11

... Figure 1. Mode 0 Timing - 11 - BICK Figure ≥32fs Figure 1 ≥40fs Figure 2 ≥48fs Figure 3 32fs or ≥48fs Figure 4 (default) ≥48fs Figure 2 BICK Figure ≥48fs Figure 3 32fs or ≥48fs Figure Rch Data [AK4145 2007/11 ...

Page 12

... Don’t care 23 Lch Data Figure 4. Mode 3 Timing - Rch Data Don’t care 1 Rch Data Don’t care Rch Data [AK4145 2007/11 ...

Page 13

... Input Level to BTSC Encoder The AK4145 is designed to be 100% modulation of L+R signal when L=R= 50% (approx. -6dBFS) signal data is input. In addition to this -6dBFS, the BTSC standard contains the pre-emphasis filter. To prevent the clipping in a BTSC encoder AK4145, following maximum input levels are recommended. The input data can be attenuated by controlling the Stereo Volume Control registers (L7-0, R7-0 bits) ...

Page 14

... If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued and returned to the volume level by the same number of clock cycles. Rev. 0.3 DEM bit De-emphasis Filter OFF Table 11. De-emphasis Filter Control (1) Figure 6. Soft Mute - 14 - (default) (2) (1) [AK4145] 2007/11 ...

Page 15

... BTSC Stereo/MONO Output Control The STR bit controls the Stereo/MONO output mode. Setting of the STR bit “1” (default) selects the BTSC stereo output mode. Setting of the STR bit “0” selects the MONO mode. In parallel control mode, the AK4145 is fixed to the stereo mode. ...

Page 16

... All commands are preceded by a START condition. After the START condition, a slave address is sent. After the AK4145 recognizes the START condition, the device interfaced to the bus waits for the slave address to be transmitted over the SDA line. If the transmitted slave address matches an address for one of the devices, the designated slave device (receiver) pulls the SDA line to LOW (ACKNOWLEDGE) ...

Page 17

... In the read mode, the slave, the AK4145 will transmit the eight bits of data, release the SDA line and monitor the line for an acknowledge acknowledge is detected, the slave will continue to transmit data acknowledge is not detected, the slave will terminate further data transmissions and await the STOP condition ...

Page 18

... The AK4145 is capable of more than one byte write operation by one sequence. After receipt of the third byte, the AK4145 generates an acknowledge, and awaits the next data again. The master can transmit more than one words instead of terminating the write cycle after the first data word is transferred. After the receipt of each data, the internal 5bits address counter is incremented by one, and the next data is taken into next address automatically. If the address exceeds TBDH prior to generating the stop condition, the address counter will “ ...

Page 19

... Therefore, if the last access (either a read or write) was to address n, the next CURRENT READ operation would access data from the address n+1. After receipt of the slave address when R/W bit set to “1”, the AK4145 generates an acknowledge, transmits 1byte data which address is set by the internal address counter and increments the internal address counter by 1. After the transmission of a data, the master can read next address’ ...

Page 20

... Do not write “1” data to the register named “0”. Rev. 0 VCLK DIF2 DIF1 DIF0 VOLC 0 FS1 FS0 ATT7 ATT6 ATT5 ATT4 [AK4145 SMUTE RSTN 0 DEM 0 STR ATT3 ATT2 ATT1 ATT0 PL3 PL2 PL1 PL0 2007/ ...

Page 21

... Common Control (default). L7-0 bits control both Lch and Rch. R7-0 bits are ignored. Rev. 0 VCLK DIF2 DIF1 DIF0 R/W R/W R/W R (Table VOLC 0 FS1 FS0 R/W R/W R/W R [AK4145 SMUTE RSTN R/W R/W R/W R DEM 0 STR R/W R/W R/W R 2007/11 ...

Page 22

... R/W R/W R/W R (Table 10 ATT7 ATT6 ATT5 ATT4 R/W R/W R/W R [AK4145 R/W R/W R/W R R/W R/W R/W R ATT3 ATT2 ATT1 ATT0 R/W R/W R/W R ...

Page 23

... Analog Ground Rev. 0.3 SYSTEM DESIGN 1 FILT CA 2 PSN A VDD CV27M 3 V COM 4 PDN VS S AK4145 5 MCLK DVDD 6 LRCK TVDD BICK 7 SCL 8 SDTI SDA Figure 16. Typical Connection Diagram - 23 - [AK4145] RF Modulator 10u 16 Analog 15 + Supply 3.3V 0.1 u 10u 14 + 0.1u 10u 13 Digital 0.1 u Supply 1.8V 12 0.1 u Digital 11 Supply 3.3V 10k 10 9 2007/11 ...

Page 24

... The modulation level of sound intermediate frequency (SIF modulator can be adjusted by the internal volume control of AK4145 (04H D7-0 ATT7-0 bits). The stereo separation can be maximized by tuning the modulation level. If the output level of AK4145 (typ: 2.2Vpp) is not sufficient for the RF modulator device, the external gain stage can be used for the extra gain. ...

Page 25

... Seating Plane NOTE: Dimension "*" does not include mold flash. ■ Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: Solder plate (Pb Free) Rev. 0.3 PACKAGE 9 8 0.65 Detail A 0.10 Epoxy [AK4145] 1.05 ± 0.05 A 0.17 ± 0.05 0.1 ± 0.1 0-10 ° 2007/11 ...

Page 26

... Rev. 0.3 MARKING AKM 4145ET XXYYY Pin #1 indication 1) Date Code : XXYYY (5 digits) 2) XX: Lot# YYY: Date Code Marketing Code : 4145ET 3) Asahi Kasei Logo [AK4145] 2007/11 ...

Page 27

... AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification. Rev. 0.3 IMPORTANT NOTICE , and AKEMD assumes no responsibility for such use, except for the use Note2 [AK4145] in any safety, life support, or Note1) 2007/11 ...

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