am79c864a Advanced Micro Devices, am79c864a Datasheet - Page 13

• Manufacturer Part Number: am79c864a
• Description: Physical Layer Controller With Scrambler Plc-s
• Manufacturer: Advanced Micro Devices

FUNCTIONAL DESCRIPTION
Node Processor Interface (NPI)
The Node Processor Interface serves as the interface
between an external Node Processor and the PLC-S.
The interface is a general purpose synchronous
interface.
The Node Processor Interface is controlled by the
NPCLK. In normal operation this clock is tied to the
BCLK. All signals of the NPI must be synchronous with
the NPCLK, that is the signals must be stable a setup
time before and a hold time after a rising edge of the
NPCLK. Figure 1 illustrates the NPI state machine.
Read Cycle
A read cycle is used by the Node Processor to read data
from a PLC-S register. Normally the PLC-S is unaf-
fected by a read, although the INTR_EVENT,
VIOL_SYM_CTR, MIN_IDLE_CTR, and LINK_ERR_
CTR registers are cleared when read.
A read cycle of one of the PLC-S registers is initiated by
the assertion of the CS signal which is sampled by the
rising edge of NPCLK. Once the CS signal is asserted
the NPADDR bus and NPRW signals are sampled. The
NPRW signal should be high for a read and low for a
write. At least one half NPCLK cycle after this edge, the
PLC-S will begin to drive the NP bus to allow the chip
driving the bus in the previous read or write cycle time to
tri-state the NP bus.
After the next rising edge of NPCLK (the second rising
edge after the assertion of CS), the data on the NP bus
will be valid. It will remain valid until the second rising
edge of NPCLK after the deassertion of CS. The PLC-S
will tri-state the NP bus within 1/2 NPCLK cycle after this
clock edge.
The timing described above will allow a read cycle every
2 NPCLK periods. However, if the Node Processor
needs to extend the read cycle and have the NP bus
valid longer than one clock cycle, it can delay the
deassertion of the CS signal. For a minimum length read
cycle (2 NPCLK periods), the Node Processor must
deassert CS a setup time before the second rising edge
of NPCLK following the assertion of CS. If CS remains
asserted for a hold time after the second rising edge of
P R E L I M I N A R Y
Am79C864A
NPCLK, again with respect to CS being asserted, the
PLC-S will continue to drive the NP bus with valid data
for two more rising edges of the NPCLK. When CS is
kept asserted beyond the initial read cycle, the read cy-
cle extends by two NPCLK periods. The CS signal is
sampled on the second and each subsequent rising
edge of NPCLK after the initial assertion of CS. The
Node Processor can indefinitely extend the read cycle
by maintaining the assertion of the CS signal. The Node
Processor must deassert and then assert the CS signal
for each unique read access.
Write Cycle
A write cycle is used by the Node Processor to write data
into a PLC-S control register. The Node Processor is
normally allowed to write to any read-write or write-only
register at any time except to the following registers
XMIT_VECTOR, VECTOR_LENGTH, TPC_LOAD_
VALUE, and TNE_LOAD_VALUE due to special
operating conditions imposed by the PLC-S in their
usage. If the Node Processor attempts a write on a read-
only register or the special registers mentioned above at
a wrong time, the PLC-S sets the NP_ERR bit in the
INTR EVENT register. The PLC-S will not modify the
contents of the register accessed.
The write cycle is very similar to the read cycle. The prin-
cipal differences are as follows:
The Node Processor must tri-state the NP bus within
one half NPCLK period after the second rising edge af-
ter the deassertion of CS. Thus, by delaying the
deassertion of the CS signal, the Node Processor can
extend the write cycle and the time it has to tri-state the
NP bus. The deassertion of the CS signal has no effect
on the PLC-S during a write cycle. The PLC-S will not
attempt to write to a selected register more than once
until the CS signal has been deasserted. Thus, to ac-
complish back to back writes, the Node Processor must
deassert the CS signal before attempting the second
write.
The NPRW signal must be low while CS is
asserted
The data to be written must be valid on the second
rising edge of NPCLK after CS is asserted
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