am79c864a Advanced Micro Devices, am79c864a Datasheet - Page 26

• Manufacturer Part Number: am79c864a
• Description: Physical Layer Controller With Scrambler Plc-s
• Manufacturer: Advanced Micro Devices

for the short LCT. For medium LCT, it has a recom-
mended value of 500 ms (A0A2 hex in 2’s complement).
Scrub Time Register (T_SCRUB)
The Scrub Time (T_SCRUB) register has address 0C
(hex). It has a recommended value of 3.5 ms. T_SCRUB
is the same as the MAC TVX time. Its use is described in
the Physical Connection Insertion Process functional
description.
Noise Time Register (NS_MAX)
The Noise Time (NS_MAX) register has address 0D
(hex). It has a recommended value of 2 ms. NS_MAX is
the maximum length of time that noise is tolerated be-
fore a connection is broken down.
Table 7 summarizes the recommended values for the
timing parameter registers. Also shown is the 2’s com-
plement, hexadecimal equivalent of the recommended
value and the timer used for the parameter.
Physical Connection Management Bit Signaling
Registers
The PLC-S contains three registers used by the PCM to
perform bit signaling. Bit signaling is the mechanism the
PCM uses to transfer information to the PCM in the
neighboring station.
Transmit Vector Register (XMIT_VECTOR)
The Transmit Vector register has address 03 (hex). It is
readable and writable. All bits of the register are cleared
with the assertion of RST. The PCM_SIGNALING bit
must not be asserted in order to write to this register. If
PCM_SIGNALING is asserted when a write is at-
tempted, the register will not be written and the
NP_ERR bit in the INTR_EVENT register will be set.
This register is readable at any time.
The Transmit Vector consists of from one to sixteen bits
of data to be transmitted to the neighboring PCM. Bits
are transmitted one at a time by the bit signaling mecha-
nism. A one bit is represented by the transmission of
Halt Line State and a zero bit by Master Line State. Bit 0
of this register is the first bit to be transmitted, then bit 1,
3-28
Parameter
C_MIN
TL_MIN
TB_MIN
T_OUT
LC_LENGTH
LC_LENGTH
T_SCRUB
NS_MAX
Table 7. Summary of PCM Timing Parameters
AMD
Recommended Register Value
Value (ms)
0.03
100
500
1.6
3.5
50
5
2
(2’s comp/hex) Timer
ECED
FFB2
FFFE
A0A2
FF6D
FF10
F676
E796
The SUPERNET 2 Family for FDDI 1994 Data Book
TPC
TPC
TPC
TPC
TPC
TPC
TPC
TNE
P R E L I M I N A R Y
Address
(hex)
0C
0D
06
07
08
09
0B
0B
etc., up to the number of bits specified in the
VECTOR_LENGTH register.
Writing this register causes PCM_SIGNALING to be as-
serted. Therefore, the VECTOR_LENGTH register
must be initialized before this register is written.
Transmit Vector Length Register
(VECTOR_LENGTH)
The Transmit Vector Length register has address 04
(hex). It is readable and writable. All bits of the register
are cleared with the assertion of RST. The PCM_SIG-
NALING bit must not be asserted in order to write to this
register. If PCM_SIGNALING is asserted when a write
is attempted, the register will not be written and the
NP_ERR bit in the INTR_EVENT register will be set.
This register is readable at any time.
Bits 15 through 4 of this register are unused. Any value
written to these bits will be ignored. These bits will al-
ways be read as zeros.
Bits 3 through 0 of this register contain the number of
bits in the XMIT_VECTOR register to transmit. The
value in this field (0 to 15) is actually one less than the
number of bits to transmit (1 to 16).
Receive Vector Register (RCV_VECTOR)
The Receive Vector register has address 16 (hex). It is
read-only.
The Receive Vector consists of from one to sixteen bits
of data received from the neighboring PCM. Bits are re-
ceived at the same time bits are being transmitted. As bit
n is being transmitted from the Transmit Vector, bit n is
received and placed in the Receive Vector register. If
Halt Line State is received, then bit n is a one, and if
Master Line State is received then bit n is a zero. Bit 0
to the number of bits specified in the VECTOR_
LENGTH register.
Although this register is readable at any time, if
PCM_SIGNALING bit is asserted when this register is
read the data may be incomplete.
Event Counters
The PLC-S contains three event counter registers and
one threshold value register (used for gathering infor-
mation about errors occurring on its associated physical
link and for monitoring Idle symbol gaps between
packets).
Violation Symbol Counter (VIOL_SYM_CTR)
The Violation Symbol Counter has address 18 (hex). It is
read-only and is cleared whenever it is read as well as
when RST is asserted. The high order 8 bits of the regis-
ter will always be read as zeros. The low order 8 bits will
contain the counter value. The VSYM_CTR bit in the
of this register is the first bit received, then bit 1, etc., up