am79c864a Advanced Micro Devices, am79c864a Datasheet - Page 33

• Manufacturer Part Number: am79c864a
• Description: Physical Layer Controller With Scrambler Plc-s
• Manufacturer: Advanced Micro Devices

The Physical Connection Insertion (PCI) State Machine
works in conjunction with the PCM State Machine. It
controls ring scrubbing and the insertion and removal of
a station on the ring.
PCM Operation
The PLC-S implements the PCM state machine as
specified in the ANSI FDDI SMT standard. By only al-
lowing a specific set of connection types, CMT secures
a deterministic ring topology, independent of the se-
quence of station power on, etc. The primary purpose
for the PCM is to enforce these allowable connections.
The local PCM announces its attachment type to the re-
mote PCM and listens for the type of attachment from
the remote PCM. If they are compatible, the local PCM
accepts the connection, reporting the type of connection
to the station configurator. Once the connection type
has been established, the two PCMs share in testing the
pair of physical links between them. If this is successful,
the link can then be configured into the ring. The bit sig-
naling protocol is implemented in a fashion which re-
duces the software processing overhead considerably
while at the same time allow enough flexibility to change
the actual pseudo code.
PCM State Machine
The PCM State machine implements the connection se-
quence for establishing the physical connection into the
ring. The state machine is as described in the SMT
document. The PCM state machine uses various timers
whose expiration values are programmable by the vari-
ous time registers. The time registers that are relevant
to the PCM state machine are the Minimum Connect
State (C_Min), Minimum Line State Transmit Time
(TL_MIN) Minimum Break (TB_Min), Signalling timeout
(T_Out), Link Confidence Test (LC_Length)and Noise
time (NS_Max). The current state of PCM is readable
through the PLC_Status_B Register.
The PCM State machine is started by PC_Start signal
from the node processor as indicated by PCM_CNTRL
bits of PLC_CNTRL_B. The PCM State machine can be
brought to the OFF state (Stop connection) also by pro-
gramming PCM_CNTRL bits of PLC_CNTRL_B.
PCM flags that are readable by the Node Processor
through the status register of PLC-S include Line State
Flag (LSF), Receive Code Flag (RCF) and Transmit
Code Flag (TCF).
Once the connection is established and the ring is
scrubbed, PCM indicates the event through the PCM
enabled bit of the INTR_EVENT register.
The function of the PCM State Machine is described in
Table 13.
Pseudo Code Bit Signaling (PCS)
As a part of the PCM process, before the connection is
established, a sequence of bits are communicated
P R E L I M I N A R Y
Am79C864A
through the physical link. These bits as defined in the
standard convey the following information:
The above information is conveyed in the first 10 bits of
the standard pseudo code bit signalling sequence. If
more bits are needed, more information up to a maxi-
mum of 16 bits can be sent through this process.
The normal operation of the PCM is as follows. When
the PCM is in the OFF state, all the parameter registers
and the configuration registers are loaded with the ap-
propriate values. The PC_Start is written into the
PLC_CNTRL_B register. The VECTOR_LENGTH reg-
ister is then written with value n-1 (n = the number of bits
to be transmitted). Next, the XMIT_VECTOR register is
written with the bit pattern which is to be transmitted.
The PCM then transitions through the BREAK, CON-
NECT and NEXT states. Note: The VECTOR_LENGTH
and XMIT_VECTOR register has to be written after
PC_STart and before TB_MIN timer expires. It then
transitions back and forth between the NEXT and the
SIGNAL states until all the bits in the XMIT_VECTOR
register are transmitted. It causes Master Line State to
be sourced to signal a zero bit and Halt Line State to be
sourced to signal a one bit. While it transmits all the bits
it also receives the corresponding bits from the remote
station and forms a Receive Vector which is stored in the
RCV_VECTOR register. When all the bits are transmit-
ted the PCM_CODE Interrupt bit is set. The Node Proc-
essor can then read the RCV_VECTOR register. ( Note:
The PCM is still in the NEXT state).
If for any reason (other than PC_Start) the PCM state
machine transitions to the BREAK state, then a
PC_Start has to be issued before the connection proc-
ess can begin again. This is to allow the VEC-
TOR_LENGTH and the XMIT_VECTOR to be
re-initialized. Also, any transition to the BREAK state
sets the PCM_BREAK interrupt and writes the reason
for the transition in the BREAK_REASON field in the
PLC_STATUS_B register.
Typically, three bits are written into the XMIT_VECTOR
register in the beginning. After they are received, the re-
ceived bits are read by the node processor to know the
connection type. Then the node processor decides if the
Normal or Escape Sequence (escape sequence is
not defined by the standard)
The type of Physical connection (Slave, Master,
Peer A or Peer B)
The acceptance of the connection
The length of the Link Confidence Test (LCT):
short, medium, long or extended
MAC for LCT
LCT Pass/Fail
MAC Loopback
MAC output connected to this PHY
AMD
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