am79c864a Advanced Micro Devices, am79c864a Datasheet - Page 22

• Manufacturer Part Number: am79c864a
• Description: Physical Layer Controller With Scrambler Plc-s
• Manufacturer: Advanced Micro Devices

PLC-S Status Register A (PLC_STATUS_A)
PLC_STATUS_A has address 10 (hex). It is read-only.
It is used to report status information to the Node Proc-
essor about the Line State Machine (LSM).
3-24
02–00
15–11 REVISION_ID
09–08 PREV_LINE_ST
07–05 LINE_ST
Addr
(Hex)
10
03
Bit
10
04
AMD
15
Name
SIGNAL_DETECT
LSM_STATE
UNKN_LINE_ST
SYM_PR_CTR
14
REVISION_ID
13
12
Definition
These bits give the revision identification. For Am79864A (PLC-S), these bits equal ‘11111’.
For Am79C864 (PLC), these bits equal ‘00000’.
This bit, when set, indicates that signal detect is deasserted. If SDO equals zero, then
SIGNAL_DETECT is one; if SDO equals one, then SIGNAL_DETECT is zero.
This field contains the value of the previous line state whenever line state changes
from Quiet Line State, Master Line State, Halt Line State or Idle Line State (ILS16,
where ILS16 is achieved after 16 idle symbols) to another line state. When the line
state changes from anything else, this field will not be updated. It is further defined as
follows:
PREV_LINE_ST
00
01
10
11
This field contains the most recently recognized Line State by the LSM. LINE_ST is
further defined as follows:
LINE_ST
000
001
010
011
100
101
110
111
This field contains the state bit of the LSM state machine.
This bit is the Unknown Line State Bit from the LSM. Since a minimum of sixteen
symbols is required to satisfy the entry conditions of a line state (four symbols in the
case of Idle Line State), the LSM uses this bit to indicate it is attempting to recognize a
new line state. This bit is set to a one when the line state is unknown and reset to a zero
when known.
This field contains the LSM Symbol Pair Counter. When the count reaches seven,
indicating eight consecutive like symbol pairs, then Current Line State is set with the
new line state and the Unknown Line State Bit is reset. Note that Idle Line State (ILS4)
is reached after just two Idle symbol pairs.
The SUPERNET 2 Family for FDDI 1994 Data Book
11
SIGNAL
DETECT
10
Table 5. PLC_STATUS_A
P R E L I M I N A R Y
PREV
LINE
ST
9
PLC_STATUS_A
Description
Quiet Line State (QLS)
Master Line State (MLS)
Halt Line State (HLS)
Idle Line State (ILS16 – achieved after 16 Idle symbols)
Description
Noise Line State (NLS)
Active Line State (ALS)
Undefined
Idle Line State (ILS4 – achieved after 4 Idle symbols)
Quiet Line State (QLS)
Master Line State (MLS)
Halt Line State (HLS)
Idle Line State (ILS16 – achieved after 16 Idle symbols)
PREV
LINE
ST
8
The PLC_STATUS_A register bit assignments are
listed in Table 5.
LINE
ST
7
LINE
ST
6
LINE
ST
5
LSM
STATE
4
UNKN
LINE
ST
3
SYM
PR
CTR
2
SYM
PR
CTR
1
15535B-10
SYM
PR
CTR
0