am79c864a Advanced Micro Devices, am79c864a Datasheet - Page 39

• Manufacturer Part Number: am79c864a
• Description: Physical Layer Controller With Scrambler Plc-s
• Manufacturer: Advanced Micro Devices

large enough to keep the system from being approved
by regulatory agencies such as the FCC.
The peaks in the radiated signal can be reduced signifi-
cantly by scrambling the transmitted signal. Scramblers
add the output of a random generator to the data signal.
The resulting signal has fewer repetitive data patterns.
Thus the occurrence and amplitude of peaks in the fre-
quency spectrum, of the transmitted signal, are greatly
reduced and the probability of a systems approval by
regulatory agencies, such as the FCC, is increased.
The scrambled data is descrambled, at the receiver, by
adding it to the output of another random generator. The
receiver’s random generator has the same function as
the transmitter’s random generator. Because the ran-
dom generators are the same and anything exclusive-
ORed with itself is zero, the output of the descrambler is
the original data signal.
Data
Data
where
For proper operation, the random generator in the
descrambler must be synchronized to the random gen-
erator in the scrambler, i.e., the random generators
must be in the same state with respect to the data. Be-
cause the random generators operate independently of
each other, they require synchronizing circuitry.
The descrambler synchronizes itself to the scrambler by
utilizing the following relationship.
H[n] = S_Data[n]
where
This relationship is true when Data[n-J] = Data[n-K].
The requirements for a correct H(n) are approximated
during the FDDI line states ILS, QLS, HLS and MLS.
When a line state is detected, the corresponding correct
data can be deduced. The proper setting for the random
generator can be derived from Data and S_Data.
If A
The X3T9 committee has chosen X
generator function. This can be represented as a shift
A = B Therefore
A
Data = S_Data then Data
A = S_Data
A
B = 0 and
B = D_Data = Data
Data = Original Data
S_Data = Scrambled Data
D_Data = Unscrambled Data
A = Transmitter Random Generator
B = Receiver Descrambler
H[n] = a hypothesis bit
j and i are bit delays
= Exclusive-OR Function
S_Data[n-j]
S_Data
S_Data[n-i] = Data[n]
11
B = D_Data
S_Data = A
+ X
9
as the random
P R E L I M I N A R Y
Am79C864A
register with the eleventh and ninth bits fed back to the
input of the first bit via an exclusive OR gate (Figure 4).
For this polynomial, j equals eleven and i equals nine.
Table 17 shows the line state bits and the corresponding
H bits.
The following rules apply to the descrambler. When a
line state is not detected, the input to the random gen-
erator is bit 11 exclusive-ORed with bit 9. Data is
S_Data exclusive-ORed with the random generator out-
put. When a line state is detected, Data is derived from
H in accordance with Table 17. The input to the random
generator is Data exclusive ORed with S_Data.
Scrambler
A functional diagram of the scrambler is shown in
Figure 4. It combines the output of a random generator
(X
Descrambler
The descrambler (Figure 5) combines the output of a
random generator with the scrambled data to produce
an exact copy of the original unscrambled data. The ran-
dom generator has the same function as the random
generator in the scrambler (X
The descrambler has a state-synchronizer to set the
descrambler-random generator to the same state as the
scrambler-random generator. The state-synchronizer is
enabled by SCRM_RSYNC, which is from the PLC-S
decoder. When SCRM_RSYNC is true, the decoder
has not detected a valid FDDI signal. The state-syn-
chronizer attempts to set the random generator. If
SCRM_RSYNC is false, the data is valid and the ran-
dom generator is assumed to be synchronized to the
scrambler and will remain synchronized.
The state-synchronizer monitors the scrambled data for
one of the patterns in Table 17. When there is a match,
the output data is set to the corresponding value. The
random generator’s input is the deduced output XORed
with the scrambled data input, which corresponds to the
scrambler’s random generator. When there is not a
match, the output data is the scrambled data XORed
with the random generator’s output. The random gen-
erator is open loop.
11
Line State
+ X
QLS
MLS
HLS
ILS
9
) with FDDI-encoded data via an XOR gate.
Table 17. Line States
00000000000
11111111111
00100001000
00100000000
Data
11
+ X
9
).
00000000000
11111111111
01110011100
01110000000
AMD
H
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