s71gl128nb0 Meet Spansion Inc., s71gl128nb0 Datasheet - Page 23

• Manufacturer Part Number: s71gl128nb0
• Description: Stacked Multi-chip Product Mcp 512/256/128 Megabit 32/16/8 M X 16-bit Cmos 3.0 Volt-only Mirrorbittm Page-mode Flash Memory With 32 Megabit 2m X 16-bit Psram
• Manufacturer: Meet Spansion Inc.

Device Bus Operations
Legend: L = Logic Low = V
Address, A
Notes:
1. Addresses are AMax:A0 in word mode; A
2. If WP# = V
3. D
June 14, 2004 S29GLxxxN_00A4
Read
Write (Program/Erase)
Accelerated Program
Standby
Output Disable
Reset
protected or unprotected as determined by the method described in “Write Protect (WP#)”. All sectors are
unprotected when shipped from the factory (The Secured Silicon Sector may be factory protected depending
on version ordered.)
IN
Operation
or D
Word/Byte Configuration
Requirements for Reading Array Data
IN
OUT
= Address In, D
IL
as required by command sequence, data polling, or sector protect algorithm (see Figure 2).
This section describes the requirements and use of the device bus operations,
which are initiated through the internal command register. The command register
itself does not occupy any addressable memory location. The register is a latch
used to store the commands, along with the address and data information
needed to execute the command. The contents of the register serve as inputs to
the internal state machine. The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the inputs and control levels they
require, and the resulting output. The following subsections describe each of
these operations in further detail.
The BYTE# pin controls whether the device data I/O pins operate in the byte or
word configuration. If the BYTE# pin is set at logic ‘1’, the device is in word con-
figuration, DQ0–DQ15 are active and controlled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only
data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/
O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the
LSB (A-1) address function.
To read array data from the outputs, the system must drive the CE# and OE#
pins to V
control and gates array data to the output pins. WE# should remain at V
, the first or last sector group remains protected. If WP# = V
V
0.3 V
CE#
CC
X
L
L
L
L
IL
IL
±
. CE# is the power control and selects the device. OE# is the output
A d v a n c e
, H = Logic High = V
IN
= Data In, D
OE#
H
H
H
X
X
L
WE
#
H
X
H
X
L
L
Table 1. Device Bus Operations
S29GLxxxN MirrorBit
Max
RESET#
OUT
V
0.3 V
I n f o r m a t i o n
CC
:A-1 in byte mode. Sector addresses are A
H
H
H
H
L
IH
= Data Out
±
, V
ID
(Note 2)
(Note 2)
= 11.5–12.5 V, V
WP#
X
X
X
X
TM
Flash Family
ACC
V
X
X
H
X
X
HH
HH
Addresses
(Note 2)
= 11.5–12.5V, X = Don’t Care, SA = Sector
A
A
A
X
X
X
IN
IN
IN
IH
, the first or last sector will be
(Note 3)
(Note 3)
High-Z
High-Z
High-Z
DQ0–
D
DQ7
OUT
Max
:A16 in both modes.
IH
.
BYTE#
High-Z
High-Z
High-Z
= V
(Note
(Note
D
3)
3)
OUT
IH
DQ8–DQ15
DQ15 = A-1
DQ8–DQ14
= High-Z,
BYTE#
High-Z
High-Z
High-Z
= V
IL
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