s71ws512ne0bfwzz Meet Spansion Inc., s71ws512ne0bfwzz Datasheet - Page 103

• Manufacturer Part Number: s71ws512ne0bfwzz
• Description: Stacked Multi-chip Product Mcp Flash Memoy And Psram Cmos 1.8 Volt, Simultaneous Operation, Burst Mode Flash Memory And Pseudo-static Ram
• Manufacturer: Meet Spansion Inc.

FUNCTIONAL DESCRIPTION (Continued)
June 28, 2004 S71WS512NE0BFWZZ_00_A1
Latency
OE# or WE#
WAIT#
WAIT#
WAIT#
WAIT#
WAIT#
WAIT#
ADDRESS
DQ [Out]
DQ [In]
DQ [Out]
DQ [In]
DQ [Out]
DQ [In]
CLK
ADV#
CE#1
Read Latency (RL) is the number of clock cycles between the address being latched
and first read data becoming available during synchronous burst read operation.
It is set through CR Set sequence after power-up. Once specific RL is set through
CR Set sequence, write latency, that is the number of clock cycles between address
being latched and first write data being latched, is automatically set to RL-1. The
burst operation is always started after fixed latency with respect to Read Latency
set in CR.
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Valid
P r e l i m i n a r y
0
RL=3
RL=4
RL=5
1
128Mb pSRAM
D1
2
Q1
D2
D1
3
Q2
Q1
D3
D2
D1
4
Q3
Q2
Q1
D4
D3
D2
5
Q4
Q3
Q2
D5
D4
D3
6
Q5
D5
Q4
D5
Q3
D4
103