s71ws512ne0bfwzz Meet Spansion Inc., s71ws512ne0bfwzz Datasheet - Page 49

• Manufacturer Part Number: s71ws512ne0bfwzz
• Description: Stacked Multi-chip Product Mcp Flash Memoy And Psram Cmos 1.8 Volt, Simultaneous Operation, Burst Mode Flash Memory And Pseudo-static Ram
• Manufacturer: Meet Spansion Inc.

Command Definitions
June 28, 2004 S71WS512NE0BFWZZ_00_A1
Reading Array Data
Set Configuration Register Command Sequence
Writing specific address and data commands or sequences into the command
register initiates device operations. The
defines the valid register command sequences. Writing incorrect address and
data values or writing them in the improper sequence may place the device in an
unknown state. The system must write the reset command to return the device
to reading array data. Refer to
acteristics—Asynchronous”
The device is automatically set to reading asynchronous array data after device
power-up. No commands are required to retrieve data in asynchronous mode.
Each bank is ready to read array data after completing an Embedded Program or
Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the corresponding bank
enters the erase-suspend-read mode, after which the system can read data from
any non-erase-suspended sector within the same bank. After completing a pro-
gramming operation in the Erase Suspend mode, the system may once again
read array data from any non-erase-suspended sector within the same bank. See
the
After the device accepts a Program Suspend command, the corresponding bank
enters the program-suspend-read mode, after which the system can read data
from any non-program-suspended sector within the same bank. See the
gram Suspend/Program Resume
The system must issue the reset command to return a bank to the read (or erase-
suspend-read) mode if DQ5 goes high during an active program or erase opera-
tion, or if the bank is in the autoselect mode. See the
for more information. If DQ1 goes high during Write Buffer Programming, the
system must issue the Write Buffer Abort Reset command.
See also
and
formation. The Asynchronous Read and Synchronous/Burst Read tables provide
the read parameters, and
The device uses a configuration register to set the various burst parameters:
number of wait states, burst read mode, active clock edge, RDY configuration,
and synchronous mode active (see
ister must be set before the device will enter burst mode. On power up or reset,
the device is set in asynchronous read mode and the configuration register is re-
set. The configuration register is not reset after deasserting CE#.
The configuration register is loaded with a four-cycle command sequence. The
first two cycles are standard unlock sequences. On the third cycle, the data
should be D0h and address bits should be 555h. During the fourth cycle, the con-
figuration code should be entered onto the data bus with the address bus set to
address 000h. Once the data has been programmed into the configuration regis-
ter, a software reset command is required to set the device into the correct state.
The device will power up or after a hardware reset with the default setting, which
is in asynchronous mode. The register must be set before the device can enter
"Erase Suspend/Erase Resume
"Requirements for Synchronous (Burst) Read
"Requirements for Asynchronous Read Operation
A d v a n c e
S29WSxxxN MirrorBit™ Flash Family For Multi-chip Products (MCP)
Figure
I n f o r m a t i o n
for timing diagrams.
“AC Characteristics—Synchronous”
Commands" section for more information.
13,
Commands" section for more information.
Figure 16
Figure
"Command Definition
14, and
for details). The configuration reg-
Operation" section for more in-
Figure 18
"Reset
(Non-Burst)" section
Command" section
Summary" section
show the timings.
and
“AC Char-
"Pro-
49