s71ws512ne0bfwzz Meet Spansion Inc., s71ws512ne0bfwzz Datasheet - Page 124

• Manufacturer Part Number: s71ws512ne0bfwzz
• Description: Stacked Multi-chip Product Mcp Flash Memoy And Psram Cmos 1.8 Volt, Simultaneous Operation, Burst Mode Flash Memory And Pseudo-static Ram
• Manufacturer: Meet Spansion Inc.

TIMING DIAGRAMS (Continued)
Notes
Notes
124
Asynchronous Read / Write Timing #1-1 (CE#1 Control)
Asynchronous Read / Write Timing #1-2 (CE#1 / WE# / OE# Control)
ADDRESS
ADDRESS
DQ
DQ
UB#, LB#
UB#, LB#
CE#1
WE#
OE#
CE#1
WE#
OE#
*1: This timing diagram assumes CE2=H and ADV#=L.
*2: Write address is valid from either CE#1 or WE# of last falling edge.
*1: This timing diagram assumes CE2=H and ADV#=L.
*2: OE# can be fixed Low during write operation if it is CE#1 controlled write at Read-Write-Read sequence.
READ DATA OUTPUT
READ DATA OUTPUT
t
t
CHAH
CHAH
t
t
CP
CP
t
t
OH
OH
t
t
t
t
CHZ
CHZ
OHCL
OHCL
t
t
AS
AS
WRITE ADDRESS
WRITE ADDRESS
t
t
CW
t
t
WRITE DATA INPUT
WP
WC
WC
WRITE DATA INPUT
t
DS
128Mb pSRAM
t
DS
P r e l i m i n a r y
t
t
t
WRC
WR
DH
t
DH
t
t
CP
CP
t
t
ASC
ASC
t
CLZ
t
READ ADDRESS
t
READ ADDRESS
t
OLZ
CE
CE
READ DATA OUTPUT
t
OE
S71WS512NE0BFWZZ_00_A1 June 28, 2004
t
t
RC
RC
t
t
t
OH
CHAH
CHAH
t
OH