ocx256 ETC-unknow, ocx256 Datasheet - Page 18

• Manufacturer Part Number: ocx256
• Description: Ocx256 Crosspoint Switch
• Manufacturer: ETC-unknow

1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
I [3:0]
OCX256 Crosspoint Switch—Advanced Datasheet
18
BB
X
X
X
X
X
X
X
X
BA
X
X
X
X
X
X
X
X
B9
X
X
X
X
X
X
X
X
B8
X
X
X
X
X
X
X
X
B7
X
X
X
X
X
X
X
X
Table 8
Output Address Disconnect Input
Output Address Connect with
Output Address Connect—no
Input Address
A6-A0
[Rev. 2.0] 3/21/02
X
X
X
X
JTAG Instructions (Continued)
and Output
ImpliedDisconnect
ImpliedDisconnect
Set the JTAG
Address Register
Device ID out
Reset Output Buffer
and Crosspoint
Array
Set RCE Bit
Bypass
Instruction
Disconnect the Crosspoint cell at the Input location
specified at the JTAG Address Register and the Output
location specified in the Disconnect JTAG instruction
(A6-A0).
All other connections from the same input address or
to the same output address remain the same.
Connects the Crosspoint cell at the Input location
specified on the JTAG Address Register and the output
location specified in the Connect JTAG instruction
(A6-A0).
All other connections from the same Input address or
the same Output address are set to no-connects.
NOTE: This instruction increments the JTAG Address
Register (Input address).
Connects the Crosspoint cell at the Input address
specified in the JTAG Address Register and the Output
address specified in the Connect JTAG instruction
(A6-A0).
All connections to the same output address are set to
“no connect” while all other connections from the
same input remain the same as before.
Sets the 7-bit JTAG Address Register with the 7-bit
address (A6-A0) of the JTAG Instruction Register. The
7-bit address of the JTAG Address Register becomes
the Input port address for Crosspoint Access.
Serialize the device ID and revision history out to
TDO. ID for the OCX256 is 0x0000C89F
Resets the Crosspoint Array to no-connects. Sets the
Output buffer to Flow-through mode with Output
Enabled. The device ID is serialized to TDO.
Sets the RCE bit of the Mode Control Register with the
JTAG instruction bit A0.
To turn ON the RCE bit, encode bit A0 to 1.
To turn OFF the RCE bit, encode bit A0 to 0.
Places device in a mode to pass TDI data to TDO with
one clock delay. Used for programming and testing
devices through serial connected JTAG controls.
Fairchild Semiconductor
Description