ocx256 ETC-unknow, ocx256 Datasheet - Page 20

• Manufacturer Part Number: ocx256
• Description: Ocx256 Crosspoint Switch
• Manufacturer: ETC-unknow

OCX256 Crosspoint Switch—Advanced Datasheet
1.6 Device Reset Options
20
The power-on reset, RapidConfigure reset, hardware reset, and JTAG reset functions will program the
output buffers to flow-through mode (with Global Clock selected), and Output Enabled (ON). JTAG can
be reset via the TRST# pin or by clocking five consecutive one to the TMS pin. The hardware reset pin
can be done accomplished through the HW_RST# pin (active low). RC reset can be accomplished by
applying the RC instruction 1101 to the RCI[3:0] pins.
1. TLR = Test Logic Reset state.
Hardware Reset
RapidConfigure
Programming
JTAG Reset
Interface
Reset
Power-on Reset
HW_RST# (low pulse)
1. Low Pulse on TRST#
2. TMS high for 5
TCLK cycles
3. Device Reset
(instruction 1101)
4. Reset Crosspoint
Array (instruction 0010)
1. Device reset
(instruction 1101)
2. Reset Crosspoint
Array (instruction 0010)
Reset Method
[Rev. 2.0] 3/21/02
Table 11
Unchanged
Unchanged
Unchanged
Unchanged
Output
Ports
Device Reset Options
OP
OP
OP
OP
Unchanged
Unchanged
Matrix
Switch
NC
NC
NC
NC
NC
NC
(RC Enabled)
(RC Enabled)
(RC Enabled)
(RC Enabled)
RCE Mode
Unchanged
Unchanged
Unchanged
Unchanged
Control
1
1
1
1
Fairchild Semiconductor
JTAG TAP
Unchanged
Unchanged
Unchanged
TLR
TLR
TLR
TLR
TLR
1