ocx256 ETC-unknow, ocx256 Datasheet - Page 21

• Manufacturer Part Number: ocx256
• Description: Ocx256 Crosspoint Switch
• Manufacturer: ETC-unknow

2. Pin Description
Fairchild Semiconductor
NOTES:
INPP[127:0]
INN[127:0]
OUTP[127:0]
OUTN[127:0]
CLKP
CLKN
OE#
HW_RST#
UPDATE#
RCA[6:0]
RCB[6:0]
RCO[4:0]
RCI[3:0]
RC_CLK#
RC_EN#
TCK
TMS
TDI
TRST#
TDO
V
V
V
V
DD
DD
DD
SS
Pin Name
.CORE
.PAD
.IN
1. Dedicated differential input buffers can receive both LVDS and LVPECL voltage levels using
3. The LVTTL control, JTAG pins, and differential input ports are 3.3V—they are not 5V tolerant.
4. The differential output pins powered from 2.5V are 3.3V tolerant.
2. V
(1, 3)
(2)
3.3V supply.
DD
.PAD is 2.5V for OCX256L or 3.3V for OCX256P.
# of Pins
128
128
128
128
100
111
15
16
1
1
1
1
1
7
7
5
4
1
1
1
1
1
1
1
Table 12
2.5V or 3.3V Power Differential Output Buffer Voltage
2.5V Power
3.3V Power
Ground
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
OCX256 Crosspoint Switch—Advanced Datasheet
Type
Input
Input
[Rev. 2.0] 3/21/02
Power and Ground Pins
OCX256 Pin Description
JTAG Pins
RC Pins
Inverting differential input signals
JTAG Test Data Out
Core Voltage
LVTTL Control pins Voltage and Differential Input
Non-inverting differential input signals
Non-inverting differential input signals
Inverting differential input signals
Non-inverting differential Global Clock
Inverting differential Global Clock
Global Output Enable
Hardware Reset
Global Update
RapidConfigure Address A
RapidConfigure Address B
RapidConfigure Readback
RapidConfigure Instruction Bits
RapidConfigure Clock
RapidConfigure Cycle Enable
JTAG Test Clock
JTAG Test Mode Select
JTAG Test Data In
JTAG Test Reset
Buffer Voltage
Ground
Description
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